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Advanced ITC Presentation. A. Pogiel J. Rajski J. Tyszer. Motivation. Reliable test response compactor. volume reduction higher than scan chains / channels ratio high observability of scan cells for wide range of X-profiles design simplicity minimum control information. Outline.

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Advanced itc presentation

Advanced ITC Presentation

A. PogielJ. Rajski

J. Tyszer


Motivation
Motivation

Reliable test response compactor

  • volume reduction higher than scan chains / channels ratio

  • high observability of scan cells for wide range of X-profiles

  • design simplicity

  • minimum control information


Outline
Outline

  • EDT environment

  • Compactor architecture

  • Unknown states

  • Scan chain selection

  • Experimental results

  • Fault diagnosis

  • Conclusions


Edt architecture

Compactedresponses

Compressedpatterns

EDT architecture

  • Scan

  • Deterministic patterns

  • Embedded test

  • Selective compaction

  • Direct diagnosis

X-control

ATE

ATE


Linear selector

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

10

11

0

Linear selector


Synthesis algorithm
Synthesis algorithm

  • Generate randomly a polynomial

  • Verify sharing of mask bits

  • Determine rank

  • Repeat 1÷3 for several polynomials

  • Accept poly with the highest rank

  • Repeat 1÷5 for all outputs


Linear independence
Linear independence

32 mask bits

specified bits

New

DAC 2001


Encoding efficiency

64

128

192

256

Encoding efficiency

Scan chains:

mask bits


Diagnostic resolution
Diagnostic resolution

Overdrive: 8

1000 single stuck-at faults selected randomly

The smallest mask register


Conclusions
Conclusions

  • Compression higher than scan chains / channels ratio

  • Programmable scan selector

  • High observability of scan errors

  • Immune to high X-fill rates

  • Proven on industrial designs


Advanced itc presentation

Dariusz Czysz, Janusz Rajski, Jerzy Tyszer

Second Example

Advanced ITC

Presentation


Purpose
purpose

Low power scheme compatible with test compression

reduced switching during all scan operations

preserved test quality

accelerated scan shifting


Outline1
outline

  • EDT environment

  • Low power test architecture

  • Scan shift-in operations

  • Power aware decompressor

  • Capture and scan shift-out

  • Experimental results

  • Conclusions


Motivation1
motivation

100 scan chains

0.9M gates

45K scan cells

Test patterns

Scan chains observing faults


Control data encoding
control data encoding

0

1

  • Constants provided on a per pattern basis

  • Asserting all variables turn off low power test

c1 + c3 + c7 = 0

c2 + c4 + c7 = 1

c3 + c5 + c6 = 0

cn cn-1 … c2 c1 c0


Clock gater control data
clock gater control data

Specified bits refer to bits provided by scan to shut off flip-flops


Experimental results filling chains

Load

Unload

Capture

experimental results – filling chains

WTM [%]

WSA [%]

D1

D2

D3

D4

Constant

Shadow register

Combined


Filling chains clock gating
filling chains & clock gating

Reduction [%]

D1

D2

D3

D4

Load

Unload

Capture

Capture – only clock gaters


Conclusions1
conclusions

  • EDT can deliver low power tests

  • No impact on quality

  • Significant reduction of test power in shift

  • Flexible trade-offs

    • power efficiency

    • compression

    • test application time