Mountain-Mover: An Intuitive Logic Shifting Heuristic for Improving Timing Slack Violating Paths

Mountain-Mover: An Intuitive Logic Shifting Heuristic for Improving Timing Slack Violating Paths

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## Mountain-Mover: An Intuitive Logic Shifting Heuristic for Improving Timing Slack Violating Paths

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**Mountain-Mover: An Intuitive Logic Shifting Heuristic for**Improving Timing Slack Violating Paths Xing Wei , Wai-Chung Tang , Yu-Liang Wu Department of Computer Science and Engineering The Chinese University of HongKong {xwei,wctang,ylw}@cse.cuhk.edu.hk Cliff Sze , Charles Alpert IBM Austin Research Center 11501 Burnet Road, Austin, TX 78758 {csze, alpert}@us.ibm.com ASPDAC 2013**Outline**• Introduction • The Mountain Mover Heuristic • Preliminaries and problem definition • Post-placement timing optimization using logic rewiring • Experimental results • Conclusion**Introduction**• Traditionally, logic synthesis is done prior to physical synthesis which includes placement, routing and placement-based timing optimization [2]. • However, under modern sub-micron VLSI technology, wire delay dominates the total path delay. • It is observed that for industrial designs many critical paths fail to close on timing even after physical synthesis such as path straightening, buffering, Vt optimization and gate sizing.**Introduction**• Increasing wire delaygreatly increases the importance of the cell placement problem. • As a result, placement engine has become the key player for timing optimization during physical synthesis of the design flow. • In fact, multiple rounds of placement and timing optimization have to be iterated in order to identify true timing-critical paths which require an incremental placement engine to straighten them. • Thus, post-placement logic synthesis is a must in order to further improve the path delay.**The Mountain Mover Heuristic**• Design a heuristic being able to make decisions based on the whole timing picture during this post-placement logic synthesis, which avoids lots of futile logic restructures and makes the flow efficient. • We build a slack distribution graph to help guide logic rewiring technique to shift logic resource efficiently. • A slack distribution graph is a mapping from the locations of circuit cells to their slack values.**The Mountain Mover Heuristic**• An example of such a graph of an industrial customer design created by an industrial EDA tool [13]**Preliminaries and problem definition**• A circuit delay is defined as the largest signal delay among all paths from any PI to any PO. • The slack of a pin/gate is the difference (gap) between its arrival time and required arrival time. • The slack of a path is the difference (gap) between the path delay and timing constraint. • The slack of wire (i, j) is the worst slack between iand j. • The worst negative slack (WNS) of the circuit is the largest violations among all slacks in the circuit.**Logic rewiring**• Logic rewiring [14] is a circuit restructuring technique referring to the process of replacing a certain wire(TW) by another wire(AW) without changing the functionality of the circuit. • The addition and removal of wires are sometimes accompanied by changes in logic gates corresponding to the AW and TW.**Problem definition**• Given a logic netlist, its physical placement, and the timing constraints, the restructuring-based post-placement timing optimization problem is to maximize the worst slack of the circuit by (i) restructuring local circuit while preserving the functionality (ii) keeping the placement free of overlaps.**Post-placement timing optimization using logic rewiring**The overall framework: • First compute the slack of each gate/wire to construct the slack distribution graph and the slack mountain. • Run the rewiring engine [11] to remove the target wire guided by the slack distribution graph. • An overlapping-free incremental placement is performed after the logic restructuring to keep the placement legal. • Run the STA to confirm the effectiveness of the selected AW in reducing WNS..**Rule of Thumb : Boundary First**• The key idea of our scheme is to figure out a local slack mountain around the most critical path and first shift the logic from boundaries of the slack mountain to avoid getting stuck at local minimum.**Shift Logic to Less Critical Area**• When we attempt to remove a target wire, the logic rewiring engine usually suggests more than one AWs to be chosen as the alternative logic. • We use the slack distribution graph to guarantee the original logic is shifted from critical area to the less critical area.**Shift Logic to Less Critical Area**• = (xg, yg):the gradient value of TW in the slack distribution graph. • = (dx, dy) : the distance vector between TW and AW.**Shift Logic to Less Critical Area**• The first inequality makes the alternative logic located in the less critical area. • The second inequality ensures that the alternative logic is located along the gradient direction of TW.**Incremental Placement**• The incremental placement will place the replaced gate at the same location. If there is any overlap after the gate change, a new gate like AND2 or OR2 is inserted instead of replacing the original gate and the new gate is added into the circuit while keeping the placement free of overlap.**Slack Estimation**• We define the local worst negative slack (LWNS) and local total negative slack (LTNS) of a set of gates as below to help evaluate the AW candidates. • pt(·) denotes a gate set in which each gate is a primary output and belongs to the fanout cone of a gate gi in G**Slack Estimation**• We will adopt an AW if: 1. The LWNS of the rewired circuit is no worse than the original circuit. 2. The AW gains the most LTNS improvement among all AW candidates. • The first condition guarantees that the delay of the rewired circuit is not degenerated. • The second condition helps reducing the delay of all paths.**Experimental result**• Initial placements were generated by Cadence SoCEncounter 10.1 • Based on IWLS 2005 benchmark . • The Cadence 180 nm generic library is used and the circuit timing is estimated by STA with the same library.**Conclusions**• We proposed a novel framework using logic rewiring to eliminate or improve slack violating paths. • Extensive experiments upon IWLS2005 show that the scheme can improve 14.1% on circuit delays (averagely) and achieve 7X speedup compared to a recent work. • We believe that the scheme can be integrated with other strategies including both logical and physical techniques to gain a further delay reduction.