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  1. SCITT Presented by Yifat Kapach jtag course 2006

  2. What is SCITT? Static Component Interconnection Test Technology Standard IEEE P1581

  3. The acronym SCITT shows 2 important aspects: • It is about ‘static’ testing. Once in test mode it bypasses the dynamic (parametric and high frequency) properties of the component.

  4. 2. It is about component interconnection testing, verifying the connections between the device and its surroundings.

  5. A short background… • SCITT was launched in 1998. • SCITT has been jointly developed by Philips & Fujitsu. • SCITT is developed to provide a cheap test solution in combination with Boundary-Scan (not a substitute!)

  6. A complex memory is a memory with an embedded protocol or memories that need initialization before use The problem… For modern, complex memories (as Flash, SDRAM etc.) a test problem arises. • Dynamic restrictions (clusters require a high-speed clock) hamper normal interconnection test because the Boundary Scan circuit can not meet these dynamic requirements.

  7. Non-volatile memories hamper normal interconnection test because writing into the memory will destroy the functional programmed data. Testing before functionally programming the device is not feasible because of the too long testing time.

  8. Getting to the Solution… The cooperation with Boundary-Scan, in order to enable simple and efficient testing requires some Design-For-Test (DFT) adaption in these ‘complex’ memories.

  9. SCITT requires the insertion of XOR/XNOR circuits in a device. These circuits replace the normal function of a chip when in test mode. It is basically meant for board-level test.

  10. truth table

  11. The basic idea of SCITT is simple: Consider all outputs of a device as outputs of XOR/XNOR circuits. • each output function (pin) must have a unique mapping on the inputs of the device. • A fail-safe way to get in and out of test-mode is required.

  12. The patterns used as test vectors are all-0s, all-1s, walking-0 and walking-1. For an N-input memory device, this amounts to 2N+2 patterns applied through the Boundary-Scan interface. The method requires about 2N BUS cycles!

  13. In test mode a simple, static, logic (XOR/XNOR) function remains that replaces the original function of the device, as ‘seen’ from it’s pins. This logic function enables easy detection of all single stuck-at and bridging faults that may occur duringassembly.

  14. Fault Coverage For SCITT, the fault model includes: • Stuck-at faults on inputs and outputs (both stuck-at-one & stuck-at-zero) • Non-overlapping bridging faults between groups of pins: input-to-input, output-to-output or input-to-output (both wired-OR & wired-AND)

  15. For this fault model we get a perfect detection and perfect diagnosis of faults! 100%

  16. SUMMARY • SCITT test sequence writes and reads to and from the flash device without actually writing into the memory space. • SCITT needs no or almost no extra pins and requires very little silicon overhead.

  17. What is going on with SCITT… • Since 1998, Philips has worked with Fujitsu to demonstrate the technology. Fujitsu has built SCITT circuitry into 32 Mbit SDRAM and, together, they have demonstrated the viability of the technology. The work was presented at the 1999 ITC. The reaction was positive. (update written by ASSET, July 5, 2000)

  18. Addition: From the working group declarations…

  19. Scope of project: “This project will develop a standard protocol for testing the interconnection of low-cost, complex memory ICs where additional pins for testing are not available and implementation of Boundary Scan is not feasible. This protocol will describe the implementation rules for the SCITT test logic in ICs which is needed for testing and describes test mode access and exit. The project is limited to the behavioural description of the implementation and will not include the technical design for the test.”

  20. Purpose of project: “There is currently no defined, independent standard for this new test technology. Each vendor is free in the way of implementing test hardware functionality in their ICs. Without an independent standard, testability is reduced and test coverage may not be complete making the test technology less useful for users. This protocol will provide the necessary implementation rules for highest coverage and diagnosis and for test mode access and exit. It will guide IC vendors to implement and test manufacturers to support this uniform design-for-test method. The standard also allows implementation in devices other than memories. In contrast to IEEE 1149.1 standard this standard provides a static test method, requires less test pins and is lower in costs.”

  21. תם אך לא נשלם

  22. References: • part 11 slides 11.26 11.27 • •