Analytical Solutions for Heat Flow in IC Interconnects

1. Analytical Solutions for Heat Flow in IC Interconnects Kuntal Bhattacharyya Project Synopsis

2. Topics Covered • Failures in Interconnects • Reliability Concepts • Interconnect Thermal Profile • Hot Spots and Via Effects • Thermal Resistance in Interconnects • Calculation of Healing Length • Static Heat solution in (r,z,fi) plane Kuntal Bhattacharyya

3. Failures in Interconnects1,2 • Electromigration • “Current Crowding” • Increase in Joule/Self Heating • Increase in the overall line temperature Kuntal Bhattacharyya

4. Reliability Measures • Electromigration is a temperature dependent effect. Temperature control is necessary. This needs efficient Self Heating. • Current density is to be kept low. Ensured by proper Interconnect parameters ( L, R/L, C/L) • To achieve reasonable Interconnect lifetime, ITRS standards should be maintained. Kuntal Bhattacharyya

5. Assumptions Though ‘k’ is a function of temperature and position, it is assumed to be constant. All four sidewalls are considered to be adiabatic. Heat is exchanged only through the underlying substrate. Interconnect Thermal Profile3,4,5 Kuntal Bhattacharyya

6. Interconnect Heat Flow3 • Under stated assumptions and steady state conditions, the system of heat equation is k[2T/x2+ 2T/y2+ 2T/z2]+Q* =0 • The 1-D equation is2T/x2=-Q*/km The volumetric heat generation rate Q* is a factor of • Power generation rate due to RMS current. • Heat loss rate between interconnect and substrate. • The summarized interconnect heat flow equations: d2 Tline(x)/dx2=2 Tline(x)- 2 Tref(x)-2=1/ km [{kox(1+0.88 tox/w)/tmtox}- I2rmsi/ w2tm2] = I2rmsi / w2tm2 km • Significance of Tref Kuntal Bhattacharyya

7. Using the two boundary conditions T(x=0)= Tref and T(x=L)= Tref the interconnect thermal profile is obtained as T(x)= (/2)[1-{sinhx+sinh (L-x)}/sinhL]+ Tref Concept of “VIA” and its importance in heat flow. Substrate Thermal Profile3,5 Kuntal Bhattacharyya

8. Healing length LH=[ (kMH tILD/ kILD).(1/s)]0.5 Heat spread factor s=weffective/w Weffective !!!!! Temperature along wire: T(x)= T0+ Tmax [1-{cosh(x/ LH)/ cosh(L/ 2LH)}]; L/2  x  -L/2 Where  Tmax(=j2rms L 2H/ kM) Hot spots and vias Heat Profile Incorporating Via Effect6 Kuntal Bhattacharyya

9. For the 100nm technological node, W=d=2m H=tILD=0.8m kILD=kSiO2=1.4W/mK kM=kaluminum=216.5W/mK M=aluminum=2.65E-8m The length of the interconnect is the distance between the two ends of the vias Therefore, L= 50m The temperature at different points on the 50m length of the interconnect have been found and plotted using different values of “x”, that accounts for the location. X=0 is the middle of the wire. Heat profile with test parameters Kuntal Bhattacharyya

10. Rthe-e=(1/kM).L/(w.t) So, the thermal resistance per unit length: Rthe-e/L=1/(kM.w.t)= f (w, t) Interconnect thermal resistance Kuntal Bhattacharyya

11. Chip thermal resistance Kuntal Bhattacharyya

12. Heat flow in devices Should be calculated neglecting self heating. Comparison between effects of LH1 & LH2 Calculation of healing length6,7 Kuntal Bhattacharyya

13. Summary • Heat flow equations have been analyzed for an interconnect, independently, with via-effect and with substrate profile. • Thermal resistance of the interconnect and the chip has been studied. Healing length has been calculated for given device parameters. • Present and future work involves a study of the static heat conduction equation in the chip in cylindrical coordinates, and analysis of the solution. Kuntal Bhattacharyya

14. Bibliography [1] Thermal and Electrical Simulation of Deep Submicron Interconnection Systems-R.Streiter, H Wolf, Z Zhu, X Xiao, T Gessner . [2] http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm [3] K Banerjee, Pedram and Ajami, Analysis and Optimization of Thermal Issues in High-Performance VLSI, ISPD’01, April 1-4, 2001, Sonoma, California, USA . [4] Ajami, Banerjee, Pedram and Van Ginneken, Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance Ics, DAC’01, June 18-22, 2001, Las Vegas, Nevada, USA. [5] Ajami, Pedram and Banerjee, Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs, CICC 2001. [6] Chiang, Banerjee, Saraswat, A New Analytical Thermal Model For Multilevel ULSI Interconnects Incorporating Via Effects, CIS, Stanford University, CA [7] J S Brodsky, Physics-based thermal impedance models for the simulation of self-heating in semiconductor devices and circuits, Dissertation presented to the University of Florida, 1997. Kuntal Bhattacharyya