ELEN 468 Advanced Logic Design

ELEN 468Advanced Logic Design Lecture 8 Behavioral Descriptions II ELEN 468 Lecture 8

Procedural Timing Control • Delay control • Event control • Named events • “wait” construct ELEN 468 Lecture 8

Delay Control Operator (#) initial begin #0 in1 = 0; in2 = 1; #10 in3 = 1; #40 in4 = 0; in5 = 1; #60 in3 = 0; end ELEN 468 Lecture 8

… @ ( eventA or eventB ) begin … @ ( eventC ) begin … end end Event -> identifier or expression When “@” is reached Activity flow is suspended The event is monitored Other processes keep going posedge: 0->1, 0->x, x->1 negedge: 1->0, 1->x, x->0 Cannot assign value to the event variable inside the synchronized behavior Event Control Operator (@) ELEN 468 Lecture 8

module modA (…); … event sth_happens; // declaration always … ->sth_happens; // trigger event end endmodule module modB(…); … always @ (top_mod.modA.sth_happens) … endmodule Also called abstract event Declared only in module with keyword event Must be declared before it is used Event is triggered by “->” Provide high level inter-module communication without physical details Named Event ELEN 468 Lecture 8

Example of Named Event module flop_event ( clk, reset, data, q, q_bar ); input clk, reset, data; output q, q_bar; reg q; event up_edge; assign q_bar = ~q; always @ ( posedge clk ) -> up_edge; always @ ( up_edge or negedge reset ) begin if ( reset == 0 ) q = 0; else q = data; end endmodule ELEN 468 Lecture 8

module modA (…); … always begin … wait ( enable ) ra = rb; … end endmodule Activity flow is suspended if expression is false It resumes when the expression is true Other processes keep going The “wait” Construct ELEN 468 Lecture 8

// B = 0 at time 0 // B = 1 at time 4 … #5 A = B; // A = 1 C = D; … A = #5 B; // A = 0 C = D; … A = @(enable) B; C = D; … A = @(named_event) B; C= D; … If timing control operator(#,@) on LHS Blocking delay RHS evaluated at (#,@) Assignment at (#,@) If timing control operator(#,@) on RHS Intra-assignment delay RHS evaluated immediately Assignment at (#,@) Intra-assignment Delay: Blocking Assignment ELEN 468 Lecture 8

alwaysbegin @ ( posedge clk ) G <= @ (bus) acc; C <= D; // not blocked end Sampling RHS immediately in the latest cycle Wait for time control to execute assignment Subsequent assignments are not blocked Intra-assignment Delay: Non-blocking Assignment In 1st cycle, “acc” is sampled What if no “bus” change in the same cycle? In next cycle, “acc” is sampled again Value of “acc” from previous cycle is overwritten Warning message ELEN 468 Lecture 8

module or8( y, a, b ); input [7:0] a, b; output [7:0] y; reg [7:0] y; initial begin assign y = a | b; end endmodule Model combinational logic by one-shot (initial) behavior Valid Not preferred Not accepted by synthesis tool Be Cautious ELEN 468 Lecture 8

Example initial begin a = #10 1; b = #2 0; c = #3 1; end initial begin d <= #10 1; e <= #2 0; f <= #3 1; end t a b c d e f 0 x x x x x x 2 x x x x 0 x 3 x x x x 0 1 10 1 x x 1 0 1 12 1 0 x 1 0 1 15 1 0 1 1 0 1 ELEN 468 Lecture 8

Event control is blocked Tell the Differences always @ (a or b) y = a|b; always @ (a or b) #5 y = a|b; always @ (a or b) y = #5 a|b; always @ (a or b) y <= #5 a|b; Which one describes or gate? ELEN 468 Lecture 8

Simulation of Assignments • For each given time step • Evaluate all Right-Hand-Side • Execute blocking assignment • Execute non-blocking assignment that do not have intra-assignment timing control • Execute past non-blocking assignment that is scheduled at this time • Execute $monitor. However, $display is executed whenever it is encountered. • Increment time step ELEN 468 Lecture 8

Normally the last assignment at certain simulation time step If it triggers other blocking assignments, it is executed before the blocking assignment it triggers always … begin A <= B; end … always … begin C = @(A) D; end Simulation of Non-blocking Assignment ELEN 468 Lecture 8

Example initial begin a = 1; b = 0; a <= b; b <= a; $display(“a=%b b=%b”, a, b); end initialbegin a = 1; b = 0; a <= b; b <= a; $monitor(“a=%b b=%b”, a, b); end a=1 b=0 a=0 b=1 ELEN 468 Lecture 8

regA = repeat (5) @ ( negedge clk ) regB; begin tmp = regB; @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); regA = tmp; end Repeated Intra-assignment Delay ELEN 468 Lecture 8

module multi_assign(); reg a, b, c, d; initial begin #5 a = 1; b = 0; end always @ ( posedge a ) begin c = a; end always @ ( posedge a ) begin c = b; end always @ ( posedge a ) begin d = b; end always @ ( posedge a ) begin d = a; end endmodule Multiple assignments are made to same variable in different behavior Value depends on code order or vendor specifications Similar to race-conditions in hardware Indeterminate Assignment ELEN 468 Lecture 8

ELEN 468 Advanced Logic Design