ELEN 468 Advanced Logic Design

1. ELEN 468Advanced Logic Design Lecture 5 User-Defined Primitives ELEN 468 Lecture 5

2. Primitives • Pre-defined primitives • Total 26 pre-defined primitives • All combinational • Tri-state primitives have multiple output, others have single output • User-Defined Primitives (UDP) • Combinational or sequential • Single output • UDP vs. modules • Used to model cell library • Require less memory • Simulate faster ELEN 468 Lecture 5

3. select a mux_prim out b UDP: Combinational Behavior primitive mux_prim ( out, select, a, b ); output out; input select, a, b; table // select a b : out 0 0 0 : 0; // Each column -> a port 0 0 1 : 0; // Last column -> single output 0 0 x : 0; // Input port column order = port list order 0 1 0 : 1; // No inout port 0 1 1 : 1; // Only 0, 1, x on input and output 0 1 x : 1; // A “z” input is treated as “x” 1 0 0 : 0; // If an input vector is not in table, output -> “x” 1 1 0 : 0; 1 x 0 : 0; 1 0 1 : 1; 1 1 1 : 1; 1 x 1 : 1; x 0 0 : 0; // Reduce pessimism x 1 1 : 1; // Without these 2 rows, output “x” for select = “x” endtable endprimitive ELEN 468 Lecture 5

4. select a mux_prim out b Shorthand Notation primitive mux_prim ( out, select, a, b ); output out; input select, a, b; table //select a b : out 0 0 ? : 0; // ? => iteration of table entry over 0, 1, x. 0 1 ? : 1; // i.e., don’t care on the input 1 ? 0 : 0; 1 ? 1 : 1; ? 0 0 : 0; ? 1 1 : 1; endtable endprimitive ELEN 468 Lecture 5

5. UDP: Sequential Behavior • In table description, n+2 columns for n input • n input columns + internal state column + output (next state) column • Output port -> reg variable ELEN 468 Lecture 5

6. Level-sensitive Behavior primitive transparent_latch(out, enable, in); output out; input enable, in; reg out; table //enable in state out/next_state 1 1 : ? : 1; 1 0 : ? : 0; 0 ? : ? : -; // ‘-’ -> no change x 0 : 0 : -; x 1 : 1 : -; endtable endprimitive enable in Transparent latch out ELEN 468 Lecture 5

7. Edge-sensitive Behavior primitive d_flop( q, clock, d ); output q; input clock, d; reg q; table // clock d state q/next_state (01) 0 : ? : 0; // Parentheses indicate signal transition (01) 1 : ? : 1; // Rising clock edge (0?) 1 : 1 : 1; (0?) 0 : 0 : 0; (?0) ? : ? : -; // Falling clock edge ? (??) : ? : -; // Steady clock endtable endprimitive clock d q d_flop ELEN 468 Lecture 5

8. Mixed Behavior primitive jk_prim(q, clk, j, k, preset, clr); output q; input clk, j, k, preset, clr; reg q; table // clk j k pre clr state q/next_state ? ? ? 0 1 : ? : 1; ? ? ? * 1 : 1 : 1; // ‘*’ -> (??) ? ? ? 1 0 : ? : 0; ? ? ? 1 * : 0 : 0; r 0 0 1 1 : ? : -; // ‘r’ -> (01) r 0 1 1 1 : ? : 0; r 1 0 1 1 : ? : 1; … … b * ? ? ? : ? : -; // b -> iterate through 0 and 1 … … endtable endprimitive ELEN 468 Lecture 5

9. Additional UDP Notations ELEN 468 Lecture 5

10. Initialization of Sequential Primitives primitive d_flop( q, clock, data ); output q; input clock, data; reg q; initial q = 0; // Set initial value of q table … … endtable endprimitive ELEN 468 Lecture 5

11. Exercises ELEN 468 Lecture 5

12. True or False • A Verilog reg variable can be the output of a pre-defined primitive, false • A Verilog net variable cannot be assigned value by continuous assignment, false • All module ports are scalars, false ELEN 468 Lecture 5

13. Find Syntax Error • reg [7:0] a, [15:0] b; • reg [7:0] a; • reg [15:0] b; • integer [7:0] count_index; • integer count_index[7:0]; ELEN 468 Lecture 5

14. Problems • If a=0010, b=1010, c=0001, what is {a,b[3],b[1],c[2],c[0]} ? 00101101 • A = 0101, B = 1001, what is • A && B ? 0 • A & (&B) ? 0101 & 0 = 0 • In UDP notations, what is the difference between ‘r’ and ‘p’? ELEN 468 Lecture 5