Integration of Modelling Tools for Parallel Optical Interconnects in a Standard EDA Design Environment

1. Integration of Modelling Toolsfor Parallel Optical Interconnectsin a Standard EDA Design Environment Michiel De Wilde, Olivier Rits, Wim Meeus, Hannes Lambrecht, Jan Van Campenhout Ghent University, Belgium IMEC EDA modelling of POI with direct CMOS-optics hybridization

2. Overview • Chip-to-chip Parallel Optical Interconnects (POI) • Concept: CMOS with hybridized optics • Integration in EDA tools • EDA support for POI elements (IC and system level)(compared to electrical interconnect) • Coherent circuit-level simulation • Analog models • Digital simulation • Timing verification: random behaviour in POI EDA modelling of POI with direct CMOS-optics hybridization

3. Concept: CMOS with hybridized optics Connector Fiber bundle Package PCB VCSELs Photodiodes Solder balls CMOS substrate (top side visible) EDA modelling of POI with direct CMOS-optics hybridization

4. POI elements Optical waveguides (POF/integrated) VCSEL technology Photodetector technology Driver & receiver circuitry Optics-CMOS hybridization IC packaging TX Clock re-sync circuitry Connectorization Waveguide routing technology EDA modelling of POI with direct CMOS-optics hybridization

5. Interconnect data flow parallel optical interconnect electrical interconnect EDA modelling of POI with direct CMOS-optics hybridization

6. EDA support for interconnections For interconnect, design tools normally provide: • Design (instantiation) of system-specific parts • pre-production Validation • post-production Testing IC level D,V & T PCB level D, V (& T) IC level D,V & T interface V interface V +pads +pads EDA modelling of POI with direct CMOS-optics hybridization

7. IC-level EDA support for interconnect • Electrical interconnect: • pads + I/O circuits • (reduced) layout view • analog & digital simulation views • Parallel optical interconnect: • VCSEL driver/photodiode receiver + flip-chip pads • design kit: similar approach EDA modelling of POI with direct CMOS-optics hybridization

8. Driver/receiver simulation model • Normal analog electrical circuits • IP protection: compiled/no real circuit given • Alternative: parameterised flowchart • Validation: comparison with compiled circuit Receiver flowchart Photocurrent input Transimpedance preamplifier Postamplifier Equalizer Decision circuit Limiting amplifier Digital output EDA modelling of POI with direct CMOS-optics hybridization

9. Post-assembly testing of optical links • JTAG Boundary Scan cells in RX/TX circuits • DC-free signal alternating on test clock: AC-JTAG EDA modelling of POI with direct CMOS-optics hybridization

10. Photonics in circuit-level simulators • Verilog-AMS and VHDL-AMS support “optical power” • Options at the interface between models: light power light power modelled device A modelled device B modelled device A modelled device B current-like approach potential-like approach • Natural choice: current-like approach, but • Kirchhoff’s first law is enforced • Photons from opposite directions would counteract each other? • Potential-like: explicit optical propagation inside models EDA modelling of POI with direct CMOS-optics hybridization

11. VCSEL modelling carrier density photon number in the kth mode (image: M.X. Jungo) • Highly nonlinear differential equation system • Spatial integration is too slow(and not possible with circuit-level simulators) EDA modelling of POI with direct CMOS-optics hybridization

12. Verilog-AMS VCSEL model in out<1:2> gnd! • Abstractions by Mena, Morikuni, Jungo: • fix the shape of mode profiles • result: spatial integration becomes static optical power per mode & fixed mode profiles • Electrical model: diode + parasitics • Convergence and numerical issues EDA modelling of POI with direct CMOS-optics hybridization

13. Photodiode modelling • Linear: electrical current vs. optical power I (mA) responsivity L I dark current L (mW) • Electrical parasitics overwhelm intrinsic response Result: only total incident light power is required EDA modelling of POI with direct CMOS-optics hybridization

14. Verilog-AMS photodiode model module pin_photodiode(in,anode,cathode); input in; inout anode, cathode; power in; electrical anode, cathode; parameter real Cdep=0, Cbo=0, Rbas=0, Resp=0, Id=0; parameter real pole=-1/(Cdep*Rbas); parameter real laplace_coeff_0=Cdep+Cbo; parameter real laplace_coeff_1=Cdep*Cbo*Rbas; charge rc; analog begin I(cathode,anode) <+ laplace_zp(Resp*Pwr(in)+Id,{},{pole,0}); Q(rc) <+ laplace_np(V(cathode,anode),{laplace_coeff_0,laplace_coeff_1},{pole,0}); end endmodule • Terminals • Model parameters • Equations describing internal state and outputs EDA modelling of POI with direct CMOS-optics hybridization

15. Parameter extraction • Photodiode model: easy • simple measurements • datasheet • VCSEL model: difficult • nonlinearity • multiple modes • temperature sensitivity + self-heating • many model parameters (>60 for only 2 modes) • datasheet not sufficient • Ideally: standardized model (~BSIM transistor model) EDA modelling of POI with direct CMOS-optics hybridization

16. Optical path • Two approaches for the optical path: Integrated waveguides Routed POF Ribbonisation Routing on flexible foil EDA modelling of POI with direct CMOS-optics hybridization

17. Optical path model • Photodiode input = S propagated VCSEL modes • Categories: interface jumps & waveguides • Interface jumps: • During simulation, multiply with 0 < h < 1 • To calculate h (statically):Fresnel diffraction of free-space propagation EDA modelling of POI with direct CMOS-optics hybridization

18. Optical misalignment VCSEL-POF coupling efficiency VCSEL diameter: 8µm, fiber core: 50µm VCSEL-POF distance (µm) Misalignment: 0µm Misalignment: 10µm Numerical aperture of POF EDA modelling of POI with direct CMOS-optics hybridization

19. Propagation in waveguides Multimode: apply raytracing Transmission of a step index POF after a 90° bend(input pattern: far field of VCSEL) Core diameter: 50µm Core diameter: 98µm Bending radius (µm) Numerical aperture of POF EDA modelling of POI with direct CMOS-optics hybridization

20. Dispersion in waveguides • POF with graded index: ~0.1ps for 1m light travels faster nearby the cladding  Dispersion is negligible here • step index POF/PCB integrated: ~100ps for 1m  Dispersion cannot be neglected anymore EDA modelling of POI with direct CMOS-optics hybridization

21. Coherent interconnect simulation (exaggerated VCSEL model parameters) EDA modelling of POI with direct CMOS-optics hybridization

22. POI simulation within a digital system • Digital views with just signal propagation • Cell with multiple views: interface correspondence vcc! in out<1:N> out in gnd! gnd! propagate over fundamental mode • Extract delays from analog simulation andannotate to digital model using SDF files • Timing verification: minimal/maximal timings required… EDA modelling of POI with direct CMOS-optics hybridization

23. Static deviations Manufacturing process fluctuations Mechanical tolerances Random noise processes VCSEL relative intensity & phase noise Receiver circuit: thermal noise Coupled noise Optical crosstalk Supply noise Substrate noise Random effects in POI EDA modelling of POI with direct CMOS-optics hybridization

24. Acknowledgements • IST Interconnect by Optics project partners • Fund for Scientific Research – Flanders (Belgium) (F.W.O.) • Research assistantship EDA modelling of POI with direct CMOS-optics hybridization

25. Summary • Chip-to-chip Parallel Optical Interconnects (POI) • Concept: CMOS with hybridized optics • Integration in EDA tools • EDA support for POI elements (IC and system level)(compared to electrical interconnect) • Coherent circuit-level simulation • Analog models • Digital simulation • Timing verification: random behaviour in POI EDA modelling of POI with direct CMOS-optics hybridization

26. Application: optimization of the POI • Choices for operating currents, analog circuit design,numerical aperture, physical dimensions… • Improvement at one place can get lost elsewhere Increase of numerical aperture of fiber better coupling less bending losses worse coupling (not to scale) Choices  parameter extraction  simulation  performance  examine the opposite direction EDA modelling of POI with direct CMOS-optics hybridization

27. CMOS substrate noise Simultaneous switching noise can disturb receiver circuits (figure: Cadence) EDA modelling of POI with direct CMOS-optics hybridization

28. Substrate noise measurement setup EDA modelling of POI with direct CMOS-optics hybridization