Memory access times. # clock cycles to send the address (say 1) #clock cycles to initiate each DRAM access (say 15) #clock cycles to transfer a word of data (say 1). Clock cycles required to access 4 words:. 1 + 4x15 + 4x1. 1 + 1x15 + 1. 1 + 1x15 + 4x1. Improving performance.
Clock cycles required to access 4 words:
1 + 4x15 + 4x1
1 + 1x15 + 1
1 + 1x15 + 4x1
2 blocks / set
4 blocks / set
8 blocks / set
Cache of 4K blocks, four word block size (or four-word cache lines), and 32-bit addresses
In a direct mapped cache, when a miss occurs, the requested block can go only at one position.
In a set-associative cache, there can be multiple positions in a set for storing each block. If all the positions are filled, which block should be replaced?