d esign and i mplementaion of a ddr sdram c ontroller for s ystem on c hip n.
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D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP PowerPoint Presentation
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D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP - PowerPoint PPT Presentation


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D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP. Magnus Själander. Contents. Double Data Rate Interfaces DDR SDRAM Architecture and Functionality DDR Memory Controller Data Resynchronization Floorplan and Place & Route Future Work Conclusion.

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Presentation Transcript
contents
Contents
  • Double Data Rate Interfaces
  • DDR SDRAM Architecture and Functionality
  • DDR Memory Controller
  • Data Resynchronization
  • Floorplan and Place & Route
  • Future Work
  • Conclusion
double data rate interfaces
Double Data Rate Interfaces

New

  • Data Transmissions on rising and falling edge
  • Data Strobe

Advantages

  • Time of Flight
  • Clock Skew
  • Pin Count
  • Bandwidth

Disadvantage

  • Synchronization
sdram architecture
SDRAM Architecture
  • Four Banks
  • Row and Column Select Lines
  • 1T Memory Cells
  • Sense Amplifiers
  • Global Data Path
ddr sdram architecture
DDR SDRAM Architecture
  • 2n-prefetch
  • Delay Lock Loop
ddr sdram improvements
DDR SDRAM Improvements
  • Long Delay in Column Decode and Data Lines
  • Added a Delay Lock Loop to Increase Clock Frequency
ddr sdram commands
DDR SDRAM Commands

Same Commands as for Standard SDRAM

  • READ
  • WRITE
  • ACTIVATE
  • PRECHARGE
  • REFRESH
  • MRS (Mode Register Set)

Added

  • EMRS (Extended MRS)
capturing the data
Capturing the Data
  • Phase Shift the Data Strobe
  • Resynchronize the Data
phase shift the data strobe
Phase Shift the Data Strobe
  • Delay Lock Loop
  • Inverter Delay
  • PCB Line Delay
  • Programmable Delay Line with Temperature Sensing
synchronization of the data
Synchronization of the Data

One Flip-Flop for each Flank to Sample

synchronization of the data continued1
Synchronization of the Data Continued

Simplified Phase Detector

future work
Future Work
  • Improved Refresh Handling
  • Attempt to Reduce Initial Latency for Bursts
  • Improved Buffer Handling
conclusion
Conclusion
  • Working Implementation
  • Smaller Changes to Improve Performance
  • Highlights Difficulties and Solutions