A Radiation Hardened by Design Approach to Solve Single Event Upsets

1. A Radiation Hardened by Design Approach to Solve Single Event Upsets 6th Military and Aerospace Programmable Logic Devices (MAPLD) International Conference David W. Jensen, Steven E. Koenck, and Alan C. Tribble Advanced Technology Center Rockwell Collins Cedar Rapids, Iowa 52498 Page #1

2. Abstract • The occurrence of single event upsets (SEUs) in electronic devices used in critical space and aviation applications has been recognized over the past 10 years to be a serious problem that can jeopardize the mission completion. As semiconductor process geometries continue to shrink, the susceptibility to radiation induced SEUs increases. Special radiation-hardened semiconductor processes have been developed and shown to be effective in mitigating radiation effects in electronic devices; however, these processes are costly and difficult to keep current with state-of-the-art process density. The Rockwell Collins Advanced Technology Center has developed concepts for a set of comprehensive SEU mitigation technologies that are suitable for implementation in standard sub-micron semiconductor processes. These concepts are based on a combination of SEU prevention and SEU tolerance that make it possible to implement complex semiconductor devices such as microprocessors that are essentially SEU immune. A key Rockwell Collins innovation is a novel multiple interconnected redundant transistor (MIRT) microelectronic logic structure. In this paper we introduce the MIRT concept and its application to several key microprocessor subsystems. Page #2

3. Military and Aerospace Platforms • Space Systems • Natural Radiation Environment Composed Mainly of Protons and Electrons • Trapped Radiation Belts, Solar Proton Events, Galactic Cosmic Rays, … • Air Systems • Natural Radiation Environment Composed Mainly of Neutrons • Maximizes at About 55,000 Feet, High Latitudes • Terrestrial Systems • Low Level Background Radiation From Galactic Cosmic Rays, Radon, … Page #3

4. Statement of the Problem • The Natural (and Hostile) Radiation Environment Poses a Significant Threat to Many Electronic Devices • Single Event Upset (SEU), Single Event Latchup (SEL), … Tribble, A. C., The Space Environment – Implications for Spacecraft Design, 2nd Ed., (Princeton, NJ: Princeton University Press, 2003). Page #4

5. An Example Hardware Solution • Redundancy • The Triplex Voting Scheme Uses Three Identical Copies of Data in Separate Memory Devices and a Series of Bit-by-Bit Comparators Coupled With a Complex Programmable Logic Device (CPLD) to Ensure Data Validity. Page #5

6. An Example Software Solution • Error Detection and Correction (EDAC) • Hamming Created Concept in 1950’s • Check Bits Provide Detection of Errors and Enable Correction • Widely Used Today Page #6

7. Pro Capable of Solving the Problem Prevents SEU’s From Corrupting Data at the System Level Con Redundancy Requires Three Times the Space to Implement Increases Size, Weight, and Power of the Resulting Device EDAC Requires Additional Processing and Data Storage Pro’s and Con’s of Past Approaches Page #7

8. What Will the Future Hold? • “The Trend of Current Design Practice Suggests That Device Density Will Continue to Double Every Two Years and That Memory Size Will Continue to Quadruple Every Two Years as Well. These Factors Along With the Ever-Decreasing Power Levels Will Cause Further Reduced Energy Thresholds in Microelectronics Semiconductor Circuits in the Years to Come. This Suggests That SEU Effects are Likely to Increase 10 Fold Every Five Years. For These Reasons, it is Conceivable That All Computer Devices – Not Just Those at Altitude – Will Need to be Protected From SEU Effects Within the Next 10 - 15 Years.” • John H. Sohn • Rockwell Collins, Air Transport Systems • Masters Thesis, Iowa State University Page #8

9. Multiple Bit Upsets (MBUs) • Scaling of Semiconductor Device Geometries Now Causing MBUs • Traditional Redundancy and EDAC Methods Ineffective for These MBUs • A Systems Approach to Mitigating MBUs in Future Devices is Required SEU Discharge Region Four 0.25 mm Transistors One 1 mm Transistor Page #9

10. Mitigation Techniques • Rockwell Collins Has Developed a Suite of Approaches to Deal With MBUs in Electronic Devices • Our Focus Today is On Multiple Independent Redundant Transistors (MIRT) Page #10

11. Multiple Independent Redundant Transistors (MIRT) • Basic Principle • The Effect of Radiation Induced Charge in CMOS Circuits is to Turn an “off” Device “on”. • MIRT Constructs Gates with Redundant Transistors That are Separated by a Specified Physical Distance • Separating Transistors and Interleaving Wiring Provides Automatic Triplex Voting Page #11

12. Operational Principle • The Amount of Physical Separation is Critical to the Concept to Insure That a Single Energetic Particle is Only Able to Cause a Single Transistor in the Gate Circuit to be Momentarily Turned “On”. • Using MIRT, Transistors Will be Separated From Each Other so That if One “Off” Device is Momentarily Turned “On”, the Two Complementary Devices will Dominate the Output • The Resulting Voltage Will be Approximately 67% of Vdd • This Should be Sufficiently Far From the Switching Point to Avoid an Upset Page #12

13. MIRT Example • NAND Circuits • The MIRT Concept Can be Applied to Virtually Any Microelectronic Circuit • Flip-Flops, Latches, Clock Networks, … NAND Voltage Divider NAND FET NAND Circuit Switch Page #13

14. MIRT Advantages • When Compared to Conventional Triplex Voted RAM MIRT Offers the Following Advantages • Smaller Footprint • Triplex Voting Requires About 350% Size Increase • MIRT Concept Alone Requires 225% Increase • MIRT Plus Other Techniques Requires Only 125% Increase • Smaller Device Dimensions /Lower Device Voltages • Increasing Separation Distance Between Transistors Provides Resilience Independent of the Sensitivity of an Individual Transistors Page #14

15. Other MIRT Features • MIRT Structures May be Implemented in Either Parallel or Serial Form. • MIRT Also Includes Separation of Isolation N-Wells For P-Channel Transistors in CMOS Circuits • This Mitigates The Common Mode Threshold Shift Affects That May Occur If The N-well Is Struck By An Energetic Particle. • This N-well Separation, Coupled With N+ Guard Ring Regions, May Also Contribute to Improved Single Event Latchup (SEL) Performance. Page #15

16. The MIRT Approach Both Prevents and Tolerates Circuit Upsets Without Tripling the Number of Devices and Without a Special Fabrication Process. We Believe That MIRT Can Enable the Fabrication of Radiation Hardened Devices at Commercial Device Costs. Summary Page #16

17. References Tribble, A. C., The Space Environment: Implications for Spacecraft Design, 2nd Ed., (Princeton, NJ: Princeton University Press, 2003). Jensen, D., “An Error Correction Code to Address Neutron Single Event Upset Errors in Semiconductor Memory,” Proc. 13th Biennial Single Event Effects Symposium, April 2002. Related Patents Single Event Upset Resistant Semiconductor Circuit Element Patent Number 6,549,443 Block Code to Efficiently Correct Adjacent Data And/Or Check Bit Errors Patent Number 6,604,222 For Additional Information • Points of Contact • Dr. David Jensen(319) 295-9676dwjensen@rockwellcollins.com • Mr. Steven Koenck(319) 295-0271sekoenck@rockwellcollins.com • Dr. Alan Tribble(319) 295-9479actribbl@rockwellcollins.com Page #17