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Connecting Æ thereal to the Montium

Connecting Æ thereal to the Montium. Tom Jongsma. Commitee: prof.dr.ir G.J.M. Smit dr.ir. A.B.J. Kokkeler J.H. Rutgers M.Sc. Beamforming. Assignment introduction. Montium Tile Processor. Requirements. Designed architecture. Designed architecture. ASIC resource usage. Application.

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Connecting Æ thereal to the Montium

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  1. Connecting Æthereal to the Montium Tom Jongsma Commitee: prof.dr.ir G.J.M. Smit dr.ir. A.B.J. Kokkeler J.H. Rutgers M.Sc.

  2. Beamforming

  3. Assignment introduction • Montium Tile Processor

  4. Requirements

  5. Designed architecture

  6. Designed architecture

  7. ASIC resource usage

  8. Application

  9. Application(2)

  10. Application(2)

  11. Performance • DTL write 2.65 MB/s • From MicroBlaze to Montium • DTL read 0.99 MB/s • From Montium to MicroBlaze • Slower, because • 2 times communication over NoC necessary • Read takes more time in DTL adapter, due to memory access

  12. Performance(2) • Streaming interface • Maximum datarate 23.6MB/s per lane • 1 clock cycle latency • Datarate dependent on communication scheme switching • 2 cycles delay when switching between communication schemes occurs • Datarate decreases to 7.97MB/s when between every transfer is switched between communication schemes

  13. Conclusions

  14. Recommendations • More IP’s with streaming interface • ADC • DAC • Streaming memory • DTL adapter improvement • Inside the CCU for higher datarates • Support for single Byte transfers

  15. Questions?

  16. FPGA resource usage

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