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  1. WP2: Radiation hard on detector power management/conversion F.Faccio, G.Blanchot, S.Michelis, C.Fuentes, B.Allongue, S.Orlandi CERN – PH-ESE

  2. Outline • WP2 objectives and work plan • Present technical status • Power distribution architecture • Demonstrator prototype components • Integration issues • Coordination with experiments • Vision for the future – short and longer term F.Faccio – CERN/PH/ESE

  3. Specificity of WP2 • Intersection with the SLHC-PP (Preparatory Phase) programme approved within the EU-FP7 • Resources are provided by both SLHC-PP and “CERN White paper” • Calendar offset with respect to other WPs to synchronize with SLHC-PP (April 07-March 11) • Resources (funds, students) planned until March 2011 only • Other collaborators within EU-FP7: RAL, Bonn University, PSI, AGH Cracow, RWTH Aachen. Some of those work on the alternative serial power distribution scheme F.Faccio – CERN/PH/ESE

  4. PS Why an R&D on power distribution • Today, power is typically provided as low voltage directly from power supplies in (or outside) the cavern. No conversion on-detector • Back of envelope calculation – for quick appreciation of the consequences • Total consumption in CMS tracker (strip + pixels) • 33 kW on active electronics, 16 kA • Power lost on cables P=RI2=33 kW (out of which 14 kW inside the tracker) • With basic “average” assumptions (cable length 10m including return, all copper cables) this is equivalent to about 300 Kg of copper in the tracker volume! Bring power + remove heat = material • SLHC trackers: 10x more channels • Impossible to linearly extrapolate the present scheme, this would result in much more material (cooling and/or cables) • Power consumption for FE electronics has to be minimized • Power has to be distributed differently • Two solutions are being explored: serial powering and distribution at higher V with local conversion. WP2 deals with the second concept F.Faccio – CERN/PH/ESE

  5. WP2 objectives • Propose a power distribution scheme based on voltage conversion and develop its prototype components • Demonstrate the feasibility of the approach • Radiation and magnetic field tolerance • Integration issues (EMC, material budget, …) • Availability of long-term supply • Acquire and spread knowledge and tools to adapt the components to evolving final specifications F.Faccio – CERN/PH/ESE

  6. WP2 work plan • Power distribution architecture • Study and compare existing converter topologies • Different inductor-based DCDC topologies, switched capacitors, piezoceramic transformers • Propose a distribution scheme using the selected topologies • Demonstrator prototype components • Develop the required radiation and magnetic field tolerant components for the selected distribution scheme • ASICs, passives if appropriate (inductors), PCB boards, shields • Integration issues • Integrate prototype components in representative detector systems F.Faccio – CERN/PH/ESE

  7. Outline • WP2 objectives and work plan • Present technical status • Power distribution architecture • Demonstrator prototype components • Integration issues • Coordination with experiments • Vision for the future – short and longer term F.Faccio – CERN/PH/ESE

  8. Power distribution architecture stave Optical link Building Blocks • Stage1: • Inductor-based buck • Vin = 10-12 V • Vout = 2.5-1.8 V • Pout = 2-4 W 10-12V Detector 2.5 V • Stage2: • On-chip switched capacitor • Vin = 2.5-1.8 V • Conversion ratio ½ or 2/3 • Iout = 20-100 mA GBT,Opto 1.25V 10-12V Stave Controller Same blocks can be combined differently to meet custom system requirements Intermediate voltage bus Proposed distribution scheme based on 2 conversion stages Example design shown for ATLAS short strip concept 10-12V F.Faccio – CERN/PH/ESE

  9. Demonstrator prototype components • Required components for the proposed distribution scheme • Stage 1 • Buck converter ASIC • Air-core inductor • Full DCDC converter board • Stage 2 • Switched capacitor IP block(s) embeddable in FE chips – same semiconductor technology F.Faccio – CERN/PH/ESE

  10. NMOS 0.25um 0.35um 0.35um PMOS 0.25um 0.25um Buck converter ASIC: technology • A survey of CMOS technologies offering both “mixed-mode low-V” and “high-V” (up to 15-20V) transistors has been carried on • 2 technologies have been selected: main (IHP 0.25um) and backup (On-semicond. 0.35um) • Prototype ASICs have been developed in both technologies F.Faccio – CERN/PH/ESE

  11. Buck converter ASIC: prototypes F.Faccio – CERN/PH/ESE

  12. AMIS2 performance • Prototype in backup technology (On-semiconductors 0.35um): “AMIS2” • Electrical performance satisfactory (peak efficiency for nominal conditions 80%) • Radiation tests with TID (X-rays) and protons (Irrad1). Functionality is maintained and performance degradation well acceptable up to the maximum radiation levels tested: 300Mrad and 5∙1015p/cm2 • Efficiency drop during X-ray irradiation correlates well with leakage current of LDMOS transistors. This effect is moderated when irradiation is performed at lower dose rate (such as in the real application) X-rays protons F.Faccio – CERN/PH/ESE

  13. IHP1 performance • Prototype in main technology (IHP 0.35um): “IHP1” • Estimated losses match measured losses • IHP1 prototype tuned for 2.5V output at 2A reaches an efficiency of 84% • Both line and load regulation characteristics are very good: better than 15 mV output voltage variation within the whole range of Vin and Iout explored • The converter operates in stable conditions over a wide range of input voltage (5V to 11V), output voltage (tested from 0.9V to 3.3V) and output current (tested up to 3.0A) • More complete prototype (IHP2) submitted in January 2010 • It integrates also the regulators and over-I protection • It still uses wire bonding F.Faccio – CERN/PH/ESE

  14. Air core inductor solenoid Custom wounded toroid PCB toroid • Tolerance to magnetic field of up to 4T imposes air core coils • Air core typical inductance values: 500 nH MAX, currently using 200 nH • Low inductance value compensated with high switch frequency • Air core coils are larger than equivalent coils that use magnetic cores, and have much larger ESR • Switching of current path in the converter implies discontinuous current in the inductor => radiated fields • Simulation and measurements of emitted field has been performed on different inductor topologies • The custom wounded toroid seems the best compromise in terms of size, emitted field and manufacturability F.Faccio – CERN/PH/ESE

  15. Full DCDC board • A standardized characterization station to measure conducted noise has been developed – design cloned in RWTH (Aachen), Fermilab and Bristol University • Several generations of prototype DCDC boards have been developed, using both commercial components or our ASICs (AMIS1 and AMIS2) • Effect of layout, parasitic components, inductor placement studied • Conducted noise radically improved with each generation • Size drastically reduced Active footprint: 20x15mm F.Faccio – CERN/PH/ESE

  16. Integration issues • Tests with TOTEM Si strip modules and ATLAS tracker upgrade prototype hybrids (with ABCN25) have been performed to explore integration issues – mainly related to EMC Shield • Susceptibility of ABCN25 hybrids (collaboration with ATLAS SCT teams in Liverpool, CERN and Geneva University) • Susceptibility measured at Liverpool with UK hybrids and setup and at CERN (with Geneva University setup) • Hybrids were found to be sensitive to E and H fields, not sensitive to conducted noise • Shielding of DCDC will be required – thin Al foil sufficient ENC<700 ENC>1000 Shielding effectively eliminates radiated noise coupling F.Faccio – CERN/PH/ESE 16

  17. Efficiency Freq (Hz) Rout (W) Switched capacitor IP block Example: Efficiency for a converter ½ in IBM 130nm Vin=1.9V, Vout=0.93V, Iout=60mA, C=100nF • Detailed study of the circuit done, with development of analytical model (conversion ratios ½, 1/3 and 2/3) • This is very useful in guiding the design of the actual converter for any specification • Prototype implementation of a ½ converter in IBM 130nm is done in collaboration with ATLAS SCT (student from AGH Cracow) • Design will be prototyped in May MPW within ATLAS SCT upgrade activity • IP block will be transferred to Imperial College for integration in CMS tracker prototype readout ASIC (CBC) in May MPW First layout of the ½ converter in 130nm – work in progress F.Faccio – CERN/PH/ESE

  18. Outline • WP2 objectives and work plan • Present technical status • Power distribution architecture • Demonstrator prototype components • Integration issues • Coordination with experiments • Vision for the future – short and longer term F.Faccio – CERN/PH/ESE

  19. Coordination with experiments • ATLAS, CMS and “common” Working Groups on powering are an efficient communication and coordination tool • We contribute regularly to the meetings with large number of talks • Direct collaboration with ATLAS and CMS • CMS tracker • Work in parallel on DCDC boards done in RWTH and CERN, with regular exchanges of results. We provide ASICs and our knowledge on board layout, converter functionality, filtering and shielding issues • Our results and contribution were fundamental to drive the choice of the CMS task force that selected DCDC option for powering their upgraded tracker • Our standardized test setup to measure conducted noise was cloned in other Institutes participating in CMS (we helped with information and documentation) • We will provide the IP block of the ½ converter based on switched capacitors • ATLAS tracker • Characterization of prototype hybrids powered with DCDC converters is done in collaboration with Liverpool and Geneva Universities • We participate in the definition of the power distribution in the prototype supermodule developed at KEK and Geneva University. We collaborate with Liverpool University for integration of DCDC converters in the prototype stave developed in the UK-US • Design of an on-chip ½ converter based on switched capacitors in collaboration with AGH Cracow • Direct expressions of interest for the converter (other than silicon strip detectors for phase2) • CMS pixel detector for phase1 upgrade (PSI, RWTH, Fermilab) • CMS HCAL for phase1 upgrade (Minnesota, Fermilab, ….) • ATLAS TileCal (Argonne Nat. Labs) F.Faccio – CERN/PH/ESE

  20. Outline • WP2 objectives and work plan • Present technical status • Power distribution architecture • Demonstrator prototype components • Integration issues • Coordination with experiments • Vision for the future – short and longer term F.Faccio – CERN/PH/ESE

  21. Vision for next year • Targets for next 12 months • Final ASIC prototype (IHP3) before the end of the year • Complete in functionality and bump-bonded to PCB board • Fully characterized for radiation • Production of a final demonstrator full converter board embedding the ASIC and the air core inductor • Demonstrate successful integration in prototype detector systems (ATLAS and CMS) • If these objectives are met, the project in its present R&D form will be completed • Hypothesis: no radiation issue found (tests for SEEs still to be performed) • Schedule depends also on availability of prototype systems from the experiments • Manpower and funding for 2011 scheduled accordingly • We loose 2 full-time engineers (fell + phD in Jan-March 2011) • Very limited funds from EU in 2011 F.Faccio – CERN/PH/ESE

  22. Summary of resources Fellows, Students Funds CERN/EU Staff 2006 0.5 Exploratory phase 2007 1.0 0.2 2008 R&D 0.2 0.5 0.4 1.0 0.8 0.5 150K 1.0 0.8 1.0 R&D phase to feasibility 0.2 0.8 0.4 170K 127K 2009 2010 1.0 1.0 0.2 0.8 0.5 1.0 250K 87K 2011 0.2 0.8 0.5 1.0 0.3 90K? 18K ? ? ? 2012 Customization, Integration, Production, Support (C,I,P,S) ? ? ? 2013 ? 2014 ? ? F.Faccio – CERN/PH/ESE

  23. Next phase (C,I,P,S) • The existence of a demonstrator, used in early prototype systems, is a necessary first step towards final integration in systems - but more work is certainly needed • Some customization, from the evolving requirements of systems, will be needed • Revision of ASIC (additional control features, possible development of multi-phase for larger currents, …) • Specific development of boards to meet size, cooling, shielding requirements of any system • Switched capacitor converter family can be developed and made available as IP blocks • Samples shall be made available for wide use in experiments (new prototype systems, but maybe also other than CMS and ATLAS) • Small production series will be needed – production-style testing to be performed • Use of samples has to be supported • Knowledge acquired during R&D shall be used to drive successful integration • EMC, cabling, definition of power supplies, system stability • It is necessary to ensure readiness for “mass production” • The development relies on availability of technologies from industry. The supply capacity has to be maintained over time • Some sub-detectors are working on “phase-1” upgrade schemes and are very interested in using the DCDC converter • They require full DCDC boards and support in their integration • CMS pixels (1000 pieces) • CMS HCAL (4000 pieces) • ATLAS TileCal (?) F.Faccio – CERN/PH/ESE