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SmartCell: A Coarse-Grained Reconfigurable Architecture for High Performance and Low Power Embedded Computing. Xinming Huang Depart. Of Electrical and Computer Engineering Worcester Polytechnic Institute xhuang@wpi.edu.

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slide1

SmartCell: A Coarse-Grained Reconfigurable Architecture for High Performance and Low Power Embedded Computing

Xinming HuangDepart. Of Electrical and Computer EngineeringWorcester Polytechnic Institutexhuang@wpi.edu

High Performance Embedded Computing WorkshopMIT Lincoln Laboratory19th September 2007

SMART CELLS - dynamically reconfigurable microsystems with kilo-processors

architecture overview

X

X

X

X

High Speed Data I/O (10s Gbps)

+

+

+

+

PE2

PE6

PE10

PE9

PE11

PE1

PE3

PE5

PE7

SRM

SRM

SRM

X

X

X

X

+

+

+

+

PE4

PE8

PE12

X

X

X

X

PE14

PE18

PE22

+

+

+

+

PE13

PE15

PE17

PE19

PE21

PE23

SRM

SRM

SRM

X

X

X

X

PE16

PE20

PE24

+

+

+

Configurable interconnects

inter-chip wireless radio

Architecture overview
  • Thousands of pico-processors interconnected with high-speed switching fabrics within a single chip
    • Goal: low-power, high-performance, reconfigurable, and applicable

SMART CELLS - dynamically reconfigurable microsystems with kilo-processors

slide3

Performance Metrics,

Technical Challenges, and Applications

Performance/Power (GOPS/Watt)

ASIC

GPGPU

SmartCell

Applicability

FPGA

Flexibility

  • Technical Challenges:
  • Low power core functions
  • Interconnections (wiring and routing)
  • Compiler (hardware/alg co-design)
  • Reliability (evolvable algorithms)

For Defense and Space Applications

  • Target Performance:
  • 1,024 ALU core
  • 100 MHz
  • 500 mW
  • 200 GOPS

SMART CELLS - dynamically reconfigurable microsystems with kilo-processors

experimental performance
Experimental Performance

Energy efficiency perspectives

Benchmark performance of FIR filters

Performances of fully

pipelined 16-tap FIR filter

  • 2 by 2 SmartCell implementation:
  • TSMC 130 nm ASIC library;
  • 1.33 mm2;
  • >500 MHz operating freq.;
  • 10~18 times more power efficient than FPGA implementations;

SMART CELLS - dynamically reconfigurable microsystems with kilo-processors