by shay amosi jasmin amitai mentor mony orbach spring 2013 n.
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Encryption/Decryption system Midterm Presentation

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By: Shay Amosi & Jasmin Amitai Mentor: Mony Orbach Spring 2013. Encryption/Decryption system Midterm Presentation. Our project. Our project goal i s to create a hardware system that encrypts the data quickly and efficiently.

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Presentation Transcript
our project
Our project
  • Our project goal is to create a hardware system that

encrypts the data quickly and efficiently.

  • The system will simulate real-time encryption

between a PC and USB using FPGA.

twofish
Twofish
  • The Twofish is a symmetric key 128-bit Block Feistel network.
  • Twofish can work with variable key length from 128 to 256 bits.
  • Twofishexhibits fast and versatile performance across most platforms.
  • The Twofish structure offers a great deal of flexibility in terms of space versus speed tradeoffs.
the twofish algorithn1
The Twofishalgorithn

The TwofishConsists of the following steps:

  • The plaintext is split into 4 words
  • Input Whitening
  • 16 rounds of the F function
  • Output Whitening
implementation methods
Implementation methods
  • Pipeline:

Good choice when it comes to performance, best for pipes that contain pure logic flow without too many stalls resulting from control lines. Requires the use of many resources.

  • Iterative:

Good choice when it comes to cost reduction, best when we are not required to meet high performance.

  • Combining both:

Good choice when we want to achieve the optimal performance under resource constraints, yet the implementation is more complex.

f

f

f

f

f

f

f

pipeline is our choice
Pipeline is our choice!

Since the goal of our project as we have defined

earlier is a high-performances, and the core of

our hardware performs many serial

permutations and logic calculations, the right

choice is to pipe our computational unit.

During the project we will have to match the

dimensions of our design to the FPGA’s size.

top level scheme
TOP LEVEL SCHEME

SRAM

Keys ROM

Fifo in

Twofish

Fifo out

Twofish control

twofish algorithem
TWOFISH ALGORITHEM

DATA IN

f

f

DATA OUT

PHT

PHT

H

H

X 16

H

H

hardware environment
Hardware environment

FPGA

TWOFISH

FIFO

IN

FIFO OUT

CTRL

hardware test
Hardware Test
  • Phase #1:

Defining a set of unique inputs as the test blocks to be encrypted and save the plaintext in a separate file.

  • Phase #2:

Encrypt the set of inputs (henceforth- Twofished blocks).

  • Phase #3:

Save the ciphered text in a separate file and compare it with the expected output. (This comparison is necessary to verify the correctness of the encryption and avoid possible double errors)

  • Phase #4:

Decrypt the Twofished blocks and compare it to the initial test blocks via automated script.

hardware test phase 1 3
Hardware Test (Phase #1-3)

PLAINTEXT

FPGA

PHASE #1

256KB

TWOFISH

FIFO

IN

256KB

FIFO OUT

PHASE #2

CTRL

CIPHERTEXT

PHASE #3

hardware test phase 4
Hardware Test (Phase #4)

CIPHERTEXT

FPGA

256KB

Comparison

TWOFISH

FIFO

IN

256KB

FIFO OUT

PHASE #4

CTRL

PLAINTEXT

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