Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Università di Parma

1. Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo CiampoliniUniversità di Parma Performance Evaluation of Ultrathin gate oxide CMOS Circuits

2. Outline • Simulation models • Designed circuit • Circuit analysis • Power dissipation • Logic Swing and Noise Margin • Frequency • Conclusions

3. Technology • Starting technology • LETI • Minimum channel length 50nm • Supply voltage 1.5V • Measurement performed on Lot 6564 wafer12in Udine University • Projected technologies • Oxide thickness from 1.5nm down to 0.9nm • Supply voltage from 1.5V down to 0.9V

4. Physical device model Compact circuit model Simulation model • Physical (DESSIS) simulation • Projection to different tox • comparison to ideal device • Circuit model • EKV non-gate-permeable core • HDL correction blocks

5. Device model vs. measurements

6. Ring oscillator • 101 stages • Gate-current effects from reasonably-sized devices (200nm X 10mm) • Gate current => CMOS architecture no longer “ratioless” • NAND gate: both static and dinamic analysis

7. tox (nm) P (mW) LS (V) f (MHz) 1.5 8.4 1.488 28.7 1.3 14.7 1.486 45.0 1.1 20.0 1.486 54.2 Ideal circuit performance 0.9 23.6 1.486 55.8 Waveforms • Period shortening • VOH lowering • VOL rising • Power dissipation increase

8. VH Power consumption • DP = <Preal> - <Pideal > • Ps = (IG,n + IG,p) · Vdd /2 • Static Power consumption due to gate current

9. Power consumption • Power consumption increase, reduced by scaling down supply voltage • Solution: oxynitride / high–k dielectric

10. Logic Swing degradation • Logic Swing degradation, reduced by scaling down supply voltage

11. Noise Margin Reduction • Logic Swing reduction • Noise Margin reduction

12. Logic Swing degradation VL VH

13. Frequency shift • Frequency shift, reduced by scaling down supply voltage

14. IDp IGp Vi Vi-1 Vi+1 IDn IGn C Frequency shift • Complex transient due to: • Additional currents tunneling through gate oxide • Reduced Logic Swing • Global effect observed: Frequency increase VL VH

15. Compact circuit model developed: Based on physical model Good fitting with measurements Effects of direct-tunneling current investigated: Power consumption increase Logic swing and noise margin degradation Frequency shift Circuit maintains its functionality, but with some non- negligible performance degradations Within the investigated range, permeable-gate devices seems to be suitable for practical applications Conclusions