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ECE 477 Design Review Team 6  Spring 2009

AJ Hartnett. David Eslinger. ECE 477 Design Review Team 6  Spring 2009. Ken Pesyna. Curt Schieler. Outline. Project overview Project-specific success criteria Block diagram Component selection rationale Packaging design Schematic and theory of operation PCB layout

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ECE 477 Design Review Team 6  Spring 2009

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  1. AJ Hartnett David Eslinger ECE 477 Design Review Team 6  Spring 2009 Ken Pesyna Curt Schieler

  2. Outline • Project overview • Project-specific success criteria • Block diagram • Component selection rationale • Packaging design • Schematic and theory of operation • PCB layout • Software design/development status • Project completion timeline • Questions / discussion

  3. Project Overview • GOAL: Measure performance of a lossless compression algorithm in an FPGA • Rice Coding is algorithm of interest, generally used in FLAC • Project will be a small device that • Compresses and stores audio input • Measures latency of compression and decompression

  4. Project-Specific Success Criteria • An ability to encode streaming audio into a FLAC format using the Rice compression algorithm • An ability to decode FLAC for playback • An ability to store data in external memory • An ability to compute latency between input audio and playback • An ability to display relevant information on an LCD

  5. Block Diagram

  6. Component Selection Rationale • FPGA design constraints • Enough logical elements for computational requirements • PLLs – 1 for SDRAM, 1 for internal clock • Enough IO pins for peripherals and debugging

  7. Component Selection Rationale • FPGA: Cyclone III • 40,000 logical elements • 4 PLLs • 80 IO pins • Dev. board available for Cyclone II • Tools available (Quartus II) • Less expensive than Cyclone II

  8. Component Selection Rationale • Microcontroller design constraints • SPI module (x2) • UART module (x2) • No need for a large amount of memory

  9. Component Selection Rationale • Microcontroller: PIC24F • 2 SPI/UART modules • 16kB memory • Familiarity

  10. Component Selection Rationale • ADC and DAC design constraints • Sampling rate of 44 kHz • 16 bits per sample • Number of pins (SPI vs. parallel)

  11. Component Selection Rationale • Audio CODEC • Programmable sampling rate (8 kHz to 96 kHz) • Programmable bits per sample (16/20/24/32) • Internal A/D and D/A • Microphone input and line level output • Used on Cyclone II dev. board

  12. Component Selection Rationale • Memory design constraints • Enough for 30 seconds of audio • Rewriteable

  13. Component Selection Rationale • Memory: SDRAM from ISSI • 8 MB • FLASH too slow • Not meant for constant rewrites • SRAM doesn’t meet size requirement

  14. Packaging Design • 1/8” plastic enclosure to provide insulation and protection for our components • 9V DC wall wart & power in port • LCD, pushbuttons, mic-in and line-out jacks • PCB: 5.2” x 4.7” Packaging: 7” x 5” x 2”

  15. Schematic/Theory of OperationAudio Input and Output Audio CODEC Mic IN Line OUT

  16. Schematic/Theory of OperationMemory FPGA SDRAM

  17. Schematic/Theory of OperationOscillator FPGA VCO

  18. Schematic/Theory of OperationConfiguration/Reset - FPGA FPGA EEPROM Reset USB Blaster

  19. Schematic/Theory of OperationConfiguration/Reset - uC Microcontroller PIC24 nMCLR JTAG

  20. Schematic/Theory of Operation FPGA Debug FPGA RS-232 Driver Level Translator DB9

  21. Schematic/Theory of OperationUser Interface LCD Pushbuttons

  22. Schematic/Theory of Operation Power Supply and Voltage Regulation 2.5V 3.3V 5V 9V DC IN 1.2V

  23. Schematic/Theory of OperationIsolated power for PLLs FPGA

  24. PCB Layout Considerations • Peripherals (Line-out, mic-in, power jack) • Near the edge of board • SDRAM near FPGA (short traces) • 4 layer board – high density around FPGA • Must be under 30 in2

  25. PCB Layout

  26. PCB Layout PWR JTAG LCD pushbuttons 5V 1.2V DB-9 RS-232 uC 3.3V 2.5V Level shifter FPGA SDRAM VCO Debug Header CODEC Mic EEPROM USB Blaster Line out

  27. PCB – Power

  28. PCB – Power Plane

  29. PCB – Ground Plane

  30. PCB – FPGA

  31. PCB – FPGA Bypass Caps

  32. PCB – FPGA Bypass Caps (1.2 V)

  33. PCB – FPGA Bypass Caps (3.3 V)

  34. PCB – FPGA Bypass Caps (1.2 V power island)

  35. PCB – FPGA Bypass Caps (2.5 V power island)

  36. PCB Layout – Config devices

  37. PCB Layout - SDRAM

  38. PCB Layout – Micro

  39. PCB Layout – Audio CODEC

  40. PCB Layout – Debug

  41. PCB Layout – Debug

  42. Software Design/Development Status

  43. Software Design/Development Status

  44. Project Completion Timeline

  45. Questions / Discussion

  46. References Wolfson Audio CODEC Block Diagram

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