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Chapter 8. Register Transfer Level. Content. Register Transfer Level (RTL) RTL in HDL Algorithmic State Machines (ASM) Design Example HDL Description of Design Example Binary Multiplier Control Logic HDL Description of Binary Multiplier Design with Multiplexers.

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chapter 8

Chapter 8

Register Transfer Level

content
Content
  • Register Transfer Level (RTL)
  • RTL in HDL
  • Algorithmic State Machines (ASM)
  • Design Example
  • HDL Description of Design Example
  • Binary Multiplier
  • Control Logic
  • HDLDescription of Binary Multiplier
  • Design with Multiplexers
register transfer level rtl
Register Transfer Level (RTL)
  • Large Digital system design – modular approach
    • modular :constructed from digital device, e.g. register, decoder, multiplexer etc.
  • Register Transfer operation
    • The information flow and processing perform on the data stored in register
  • RTL is specified by the following three components:
    • The set of register in the system
    • The operation that are performed on the data stored in the register
    • The control that supervises the sequence of operation in the system
register
Register
  • Register is constructed from F.F. and gates
  • 1 F.F. =>1 bit register
  • N F.F. =>n bit resister
  • Register can perform set, cleared, or complement
data processing in register
Data processing in register
  • performed in parallel during one clock
  • The result may replace previous data or transferred to another register
  • For example
    • counter
    • Shift register
statements of rtl
Statements of RTL
  • Transfer: R2←R1
  • Conditional statement:
    • if (T1=1) then(R2 ← R1)
    • if(T1=1)then(R2 ← R1, R1 ← R2)
  • Other
    • R1 ←R1+R2
    • R3 ←R3+1
    • R4 ←shr R4
    • R5 ← 0
rtl in hdl
RTL in HDL
  • Digital system can be described in RTL
    • By means of HDL
  • Verilog HDL
    • RTL description use a combination of behavior and data flow
the transfer statement of verilog hdl without a clock
The transfer statement of Verilog HDL (without a clock)
  • Continuous statement:
  • Procedural assignment (without a clock):
the transfer statement of verilog hdl with a clock
The transfer statement of Verilog HDL (with a clock)
  • Blocking:use “=” as transfer operator
    • executed sequentially
  • non-blocking: use “<=” as transfer operator
    • executed on parallel
hdl operators
HDLoperators
  • Arithmetic :+ 、- 、 * 、 / 、 %
  • Logical:&& 、 || 、!
  • Logic:& 、 | 、 ~ 、 ^
    • Bitwise or reduction
  • Relational:> 、 < 、 == 、 != 、 >= 、 <=
    • True or false
  • Shift: >> 、 << 、 { , }
loop statement
Loop statement
  • Repeat,Forever,While,For
  • Must appear inside an initial or always block
logic synthesis
Logic Synthesis
  • The automatic process of transforming a high-level language description such as HDL into an optimized netlist of gates that perform the operations specified by the source code
  • Designers adopt a vendor-specific style suitable for particular synthesis tools
  • HDL constructs used in RTL description can be converted into gate-level description
example of synthesis from hdl to gate structure
Example of synthesis from HDL to gate structure
  • Assign
    • assign Y = S ? I1:I0 ;
    • Is interpreted as a multiplexer of 2-to-1
  • always
    • may imply a combinational or sequential circuit
    • always @ (I1 or I0 or S)

if (S) Y=I1 ;

else Y=I0 ;

    • Always @ (posedge clock)
    • Always @ (negedge clock)
algorithmic state machine
Algorithmic State Machine
  • Logic design can be divided into two part
    • The digital circuits that perform the data processing operation
    • Control circuits that determines the sequence in which the various actions are performed
algorithmic state machine asm
Algorithmic State Machine (ASM)
  • A special flowchart that has been developed specifically to define digital hardware algorithms
  • Resembles a conventional flowchart, but is interpreted somewhat differently.
    • conventional: sequential
    • ASM:
      • sequence of even
      • timing relationship between the states of sequential controller
      • even occurs while going from one state to the next
  • Three basic elements: state box, decision box, conditional box
state box
State box

FIGURE 8.3 ASM chart state box

decision box
Decision box

FIGURE 8.4 ASM chart decision box

conditional box
Conditional box

FIGURE 8.5 ASM chart conditional box

timing consideration
Timing consideration
  • Major difference between conventional flow chart and a ASM chart is in interpreting the time relation among the various operation
  • ASM considers the entire block as one unit.
design example
Design example
  • Two F.F. E and F
  • A 4-bits binary counter A (A4,A3,A2and A1)
  • A start signal S (starting by clearing A and F)
  • S=1, increment counter
  • A3and A4 determine the sequences of operations
  • If A3 = 0, Eis clear to 0, count continues
  • If A3 = 1,Eis set to 1,then if A4 = 0, the count continues, but if A4 = 1,Fis set to 1 on next clock pulse and system stops counting
  • Then if S = 0, the system remains in the initial state, but if S = 1, the operation cycle repeats.
state table for control
State table for control
  • Two F.F. G1and G2
slide30

HDL Description

HDL Example 8-2

//RTL description of design example (Fig.8-11)

module Example_RTL (S,CLK,Cir,E,F,A);

//Specify inputs and outputs

//See block diagram Fig. 8-10

input S,CLK,Cir;

output E, F;

output [4:1]A;

//Specify system registers

reg [4:1] A; //A register

reg E, F; //E and F flip-flops

reg [1:0] pstate, nstate; //control register

//Encode the states

parameter TO = 2'b00, Tl = 2'b01, T2 = 2'b11;

//State transition for control logic

//See state diagram Fig. 8-11(a)

slide31

always@(posedge CLK or negedge Clr)

if (~Clr) pstate = TO; //Initial state

else pstate <= nstate; //Clocked operations

always @ (S or A or pstate)

case (pstate)

TO: if (S) nstate = Tl; else nstate = TO;

Tl: if (A[3] & A[4]) nstate = T2; else nstate = Tl;

T2: nstate = TO;

endcase

//Register transfer operations //See list of operation Fig.8-11(b)

always@ (posedge CLK)

case (pstate)

TO: if (S)

begin

A <= 4'bOOOO;

F <= 1'bO;

end

Tl:

begin

A <= A + 1'b1;

if (A[3]) E <= 1'bl;

else E <= 1'b0;

end

T2: F <= I'bl;

endcase

endmodule

testing the design description
Testing the design description

HDL Example 8-3

//Test bench for design example

module test_design_example;

reg S, CLK, Clr;

wire [4:1] A;

wire E, F;

//Instantiate design example

Example_RTL dsexp (S,CLK.Clr,E,F,A);

slide33

Example_RTL dsexp (S,CLK.Clr,E,F,A);

initial

begin

Cir = 0;

S = 0;

CLK = 0;

#5 Clr = 1; S = 1;

repeat (32)

begin

#5 CLK = ~ CLK;

end

end

initial

$monitor("A = %b E = %b F = %b time = %0d". A.E.F,$time);

endmodule