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April 18 2008

Electromagnetic Compatibility of Integrated Circuits (EMC of ICs). Alexandre Boyer INSA de Toulouse. April 18 2008. OUTLINE. AGENDA 9h - 12h: EMC of ICs – part I (Course) 14h - 17h: EMC of ICs – part II (Course) OBJECTIVES

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April 18 2008

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  1. Electromagnetic Compatibility of Integrated Circuits (EMC of ICs) Alexandre Boyer INSA de Toulouse April 18 2008

  2. OUTLINE • AGENDA • 9h - 12h: EMC of ICs – part I (Course) • 14h - 17h: EMC of ICs – part II (Course) • OBJECTIVES • At the end of the course, the auditor will be able to understand the origins of electromagnetic compatibility (EMC) issues at integrated circuits level, the basic knowledge to face with EMC issues, and become familiar with the most common circuit-level EMC design guidelines. • PRE REQUISITES • Basic knowledge in electrical circuits, CMOS technology,electromagnetism.

  3. OUTLINE CONTENT • Introduction • EMC Basics concepts • Emission/Susceptibility Origin • Measurement methods • EMC Models • EMC Guidelines • Conclusion / Future of EMC

  4. 1. Introduction

  5. What is EMC ? Two examples « Disturbances of flight instruments causing trajectory deviations appear when one or several passengers switch on electronic devices. » (Air et Cosmos, April 1993) 29th July 1967 : accident of the American aircraft carrier USSForrestal. The accidental launching of a rocket blew gas tank and weapon stocks, killing 135 persons and causing damages which needed 7 month reparations. Investigations showed that a radar induced on plane wiring a sufficient parasitic voltage to trigger the launching of the rocket.

  6. What is EMC ? « The ability of a device, equipment or system to function satisfactorily in its electromagnetic environment without introducing intolerable electromagnetic disturbance to anything in that environment. » • Guarantee the simultaneous operation of all nearby electric or electronic devices and the safety of users in a given electromagnetic environment • Reduce parasitic electromagnetic emission and their sensitivity or susceptibility to electromagnetic interferences • Maximum levels and methods to characterize emission and susceptibility of an equipment are defined by standards

  7. CE mark What is EMC ? Examples of EMC standards • The existence of EMC specifications is linked to the safety and robustness level that an equipment must reach. • EMC standards for automotive, aerospace, military, transport, medical, telecommunication applications, but also for commercial products • European EMC directive 89/336/EEC about electronic products EMC requirements • IEC-TC77 and CISPR : IEC technical committee related to EMC standards • For automotive applications : ISO 7637, ISO 11452, CISPR 25, SAE J1113 • For military applications : MIL-STD-461D, MIL-STD-462D • For aerospace applications : DO-160 • For integrated circuits : IEC 61963, IEC 62132

  8. Deep Deep Submicron Ultra deep Nano scale Micron Nano submicron submicron Lithography (µm) 80286 2.0 16MHz 80386 Industry z 1.0 33MH 486 66MHz Pentium 120MHz 0.3 Pentium III 0.7GHz 0.25µm 0.2 Pentium IV 3GHz 0.1 Research Pentium DualCore 2.2GHz 0.05 65nm 45nm This trend has major consequences on electronic systems safety, reliability, … and EMC 0.03 32nm Working 7nm 0.02 22nm device 0.01 83 86 89 92 95 98 01 04 07 10 13 Year Context - Technology Scale Down • Channel length divided by 2 each 18 month in the 90’s • Research has 5 year advance on industry

  9. EMC of ICs Why EMC of ICs • Until mid 90’s, IC designers had no consideration about EMC problems in their design. EMc was only handled at system and PCB levels • Many EMC problems originate from ICs (3rd origin of IC redesign !), as it is the source of noise emission and sensitivity • With technology trends (increased clock speed, chip complexity and reduced voltage), ICs are more emissive and sensitive to noise • Semiconductor manufacturers are faced with increasing customer expectations for designing low emission and highly immune ICs EMC must be handled at IC level

  10. EMC of ICs EMC of IC topics • Improve or develop EMC measurement methods to respond to new customer’s requests • Develop simulation tools to predict EMC of IC behavior • Develop design guidelines aiming at reducing emission and susceptibility levels Emission level measurement Simulation Customer’s specifications IC emission spectrum Target Frequency

  11. EMC of ICs Design issues EMC problems handled at the end of design cycle DESIGN FABRICATION Architectural Design Version n° Version n° Design Entry Design Architect EMC Measurements Compliance ? NO GO GO + 6 months + $$$$$$$$

  12. Tools Training Design Guidelines EMC of ICs Design issues EMC problems handled at the end of design cycle DESIGN Architectural Design EMC validated before fabrication Design Entry Design Architect EMC Simulations Compliance ? FABRICATION NO GO EMC compliant GO

  13. 2. EMC Basic Concepts

  14. EMC environment The “EMC” way of thinking

  15. Milli Volt Volt dBV dBµV 100 40 1 60 20 10 40 0.1 For example dBV, dBA : 1 0 20 0.01 -20 0.1 0 0.001 Extensive use of dBµV -40 0.01 -20 0.0001 0.001 -60 0.00001 -40 Specific Units Voltage units Wide dynamic range of signals in EMC → use of dB (decibel)

  16. Power (Watt) Power (dBm) 90 1 MW 1 KW 60 1 W 30 1 mW 0 Exercise: Specific units 1 µW -30 1 mV = ___ dBµV 0.1 W = ___ dBm 1 nW -60 Specific Units Power units The most common power unit is the “dBm” (dB milli-Watt)

  17. Specific Units Emission and susceptibility level units dBµV dBµV/m 80 50 Class 4 70 40 Class 5 60 30 Class 5 50 20 40 10 3M 100M 30M 1G 300K 30K 1M 10M Conducted emission level (CISPR25) Radiated emission level (CISPR25) CISPR 25 : “Radio disturbance characteristics for the protection of receivers used on board vehicles, boats, and on devices – Limits and methods of measurement”

  18. Volt Time Fourier Transform Fourier transform: principle dB Freq (Log) Fourier transform Frequency measurement Time domain measurement Invert Fourier transform Spectrum analyser Oscilloscope

  19. Fourier Transform Why Frequency domain is so important ? Time domain Frequency domain Only high level harmonics contribution appears Contribution of each harmonic appears Low level harmonics contribution User’s specification FFT

  20. -20 dB/dec -40 dB/dec FFT Evaluation of signal bandwidth Fourier Transform Fourier transform - Example 50 % duty cycle trapezoidal signal Period T = 100 ns, Tr = Tf = 2 ns

  21. Emission spectrum EMC compatible Parasitic emission (dBµV) Specification for an IC emission 80 70 Sufficient margin Aggressor IC 60 50 Measured emission 40 30 20 10 Radiated emission 0 -10 1 10 100 1000 Frequency (MHz)

  22. Not EMC compliant Customer's specified limit EMC compliant Emission spectrum Low parasitic emission is a key argument FM GSM RF 100 dBµV Supplier A 80 60 Supplier B 40 20 0 10 100 1000 Frequency(MHz)

  23. Susceptibility threshold Immunity level has to be higher than customer specification Immunity level (dBmA) Specification for board immunity Current injection limit 50 40 30 Measured immunity 20 Victim IC 10 0 -10 A very low energy produces a fault -20 -30 -40 1 10 100 1000 Frequency (MHz)

  24. Parasitic emission (dBµV) Nominal Level Safety margin Process dispersion Measurement error/dispersion Component/PCB/System Ageing Environment Design Objective Notion of margin • To ensure the electromagnetic compatibility, emission or susceptibility levels have to be lower than a nominal target … • …But it is not sufficient to a zero error probability ! • Margin are required to compensate unpredictable variations and reduce the error probability. • Margin depends on the safety level required in an application domain:

  25. Parasitic coupling mechanisms Coupling mechanisms Radiated mode – Antenna coupling Conducted mode – Common impedance coupling The EM wave propagates through the air • Loop : Magnetic field coupling • Wire : Electric field coupling Example : The VSS supply track propagates noise

  26. Parasitic coupling mechanisms Crosstalk • Parasitic coupling between nearby conductors. • Near field coupling ≠ radiated coupling Capacitive crosstalk Inductive crosstalk d d w w t t C12 L12 h C dielectric C h dielectric ground ground

  27. Impedance R,L,C vs. frequency Impedance profile of: • 50 ohms resistor Z÷10 at each decade • 100pF capacitor • 10nH inductor Z = constant • a real 100 pF SMD capacitor Z×10 at each decade

  28. Impedance Passive components – Real model Ceramic capacitor Inductor Understand EMC issues requires the knowledge of electronic device parasitics Carbon resistor

  29. l 2a Current Interconnections Interconnect parasitics PCB • Parasitic resistance • Parasitic inductance Package Bonding wires Quasi static approximation : If l < λ/20, interconnections are considered as electrically small

  30. From the electromagnetic point of view: Coaxial line Microstrip line Link to conductor geometry and material properties • From the electric point of view : lossless conductor Equivalent electrical schematic Interconnections Characteristic impedance

  31. Interconnections Impedance matching Essential for signal integrity and power transfer Not adapted: the line suffers ringing, insertion losses Adapted: the line is transparent Voltage Voltage time time

  32. Small conductor Large conductor Interconnections Characteristic impedance What is the optimum characteristic impedance for a coaxial cable ? Or ? Ideal values: • Maximum power : Z0 = 32  • Minimum loss: Z0 = 77  Cable examples: • EMC cable (compromise between power and loss) : Z0 = 50  • TV cable (minimize Loss): Z0 = 75 

  33. 50 Ω adapted equipments EMC equipments Spectrum analyzer Waveform generator Tem cell Amplifier Gtem

  34. 3. Origin of Emission and Susceptibility of ICs

  35. Personal entrainments Noise interferences System Equipments Printed circuit boards Safety systems Components Hardware fault Software failure Function Loss Two main concepts Susceptibility to EM waves Emission of EM waves

  36. Interferences EMC at system level Integrated circuits are the origin of parasitic emission and susceptibility to RF disturbances in electronic systems Emission Radiation Components Chip PCB System Noisy IC Sensitive IC Coupling System Chip Components PCB Susceptibility

  37. Source of Electromagnetic Interferences Natural disturbances (cosmic rays, thunder) Radio communications, wireless, radars,… IC Electrical Overstress IC activity Inductive loads, motors

  38. Technology trends Technology (log scale) Technology trend cost-performance microcontrollers 1m 0.35m 0.25m 0.13µm 0.18m 90nm 65nm 100nm 0.13m 45nm 32nm 90nm 32nm 22nm 45nm 22nm 5-years gap Technology trend high performance microprocessors 10nm 18nm 9nm 7nm Year 1nm 2000 2005 2010 2015 2020 Year

  39. 65 nm 90 nm 0.18 µm 130 nm 100M 500M 250M 1G 2001 2003 2005 2007 Multicore, DSP FPGA, eRam RF multiband 2µC+4DSP Mb Flash µC 32 bit µC+DSP Flash Technology trends IC tech. 0.25 µm Complexity 50M Packaging 1999 µC 16 bit

  40. Origin of parasitic emission Basic mechanisms for CMOS circuit current: CMOS inverter exemple Switching current IDD (0.1mA) VDD ISS (0.1mA) IDD (0.1mA) Vin Time Voltage Output capa VOUT ISS (0.1mA) VSS Time • Main noise sources comes from AC current sources: • Clock-driven blocks, synchronized logic • Memory read/write/refresh • I/O switching

  41. i(t) Time 50ps Origin of parasitic emission • Parasitic emission is linked to voltage drops. The current peak are not the only responsible of emission. • Inductance are responsible of the conversion of current peak to voltage drops. • Current peaks and voltage drops generate the conducted emission and also responsible of the radiated emission. Vdd Radiated Emission Vdd i(t) i(t) Vss Vss Internal switching noise Switching gates Voltage drops

  42. Volt Old process New process Time Stronger di/dt Increase parasitic noise Origin of parasitic emission Why technology scale down makes things worse ? • Current level keeps almost constant but: • Faster current switching Current di/dt Old process New process Time

  43. Ampere Vdd i(t) time Vss Ampere 1 ns 1 A Current / gate Current / Ic 0.1 mA time 0.1 ns Origin of parasitic emission Example: evaluation of switching current in an IC • 0.1 mA / Gate in 100ps • 1 Billion gates (32 Bit Micro) => 100A • 10% switching activity => 10A • Spreading of current peak (non synchronous switching) => 1A in 1ns

  44. Origin of parasitic emission Example: evaluation of supply voltage bounce L=0.6nH/mm VDD L=1nH/mm Lead = 10 mm 1 A en 1 ns Evaluate noise amplitude : Chip Lead = 10 mm VSS

  45. Origin of parasitic emission Overview of influent parameters on parasitic emission • Internal activity of the IC • Output load of the circuit • Filtering effect of IC interconnections • Filtering effects of PCB tracks and external passive components Vdd i(t) i(t) IC Internal interconnexions Load IC activity Vss PCB tracks and external passive components IC

  46. Susceptibility issues Less voltage, more IOs 1000 500 200 100 Supply (V) 5.0 Noise margin reduction 3.3 2.5 I/O supply 1.8 1.2 0.7 Core supply 45nm 0.5µ 0.35µ 0.18µ 90nm 65nm Technology

  47. Susceptibility issues Multiple parasitic electromagnetic sources

  48. Susceptibility issues More complex Ics, more levels in susceptibility Software failure Electromagnetic wave Hardware fault System failure µp mixed Function loss

  49. Susceptibility issues Desynchronisation issues • Jitter is becoming increasingly important in digital design due to rising operating frequencies. • The increase of operating frequencies of digital circuits reduces their dynamic margin EMI on supply EMI induced jitter Bit error Dynamic failure EMI induced jitter

  50. Origin of IC susceptibility Overview of influent parameters on IC susceptibility RF interferences • Filtering effects of PCB tracks and external passive components • Filtering effect of IC interconnections • Impedance of IC nodes (high Z node = high susceptibility) • Non linear effects of active devices (conversion RF signals to DC offsets !) • Block own susceptibility (noise margin, delay margin, …) Internal perceived noise Vdd IC Internal interconnexions Vss IC active devices PCB tracks and external passive components IC IC failures

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