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Twin Silicon Nanowire Field Effect Transistor (TSNWFET)

Twin Silicon Nanowire Field Effect Transistor (TSNWFET). EE235 Presentation By: Rhesa Nathanael. Nanowire FET. Motivation: Superior gate control (minimize short channel effects). High drive current. Less sensitive to process variations. Improved transport property.

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Twin Silicon Nanowire Field Effect Transistor (TSNWFET)

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  1. Twin Silicon Nanowire Field Effect Transistor(TSNWFET) EE235 Presentation By: Rhesa Nathanael

  2. Nanowire FET • Motivation: • Superior gate control (minimizeshort channel effects). • High drive current. • Less sensitive to process variations. • Improved transport property. • Twin Silicon Nanowire FET demonstrated.

  3. GAA-TSNWFET Fabrication • Fully CMOS compatible. • Highly reproducible top-down approach. 9

  4. Performance Lg=30nm dNW=10nm Tox=2nm Lg=15nm dNW=8nm Tox=3.5nm NMOS Ion=2.64mA/um Ioff=3.1nA/um PMOS Ion=1.11mA/um Ioff=5.6pA/um NMOS Ion=1.44mA/um Ioff=2.0nA/um PMOS Ion=1.94mA/um Ioff=1.0nA/um

  5. VDS=1~5mV Lg=45nm T=4.2K Ballistic transport in ballistic regime Transport Property Study dNW=10.8nm Tox=3.5nm Coulomb Oscillations  single electron tunneling (Lg=45nm, T=4.2K) Conduction quantization (Lg=125nm, up to T~60K)

  6. Size Dependence Study Why? Volume inversion dominant until dnw=4nm. Surface, phonon and back scattering dominant below dnw=4nm. Optimum point: dNW=4nm

  7. Conclusion • High performance p-type and n-type Twin Silicon Nanowire MOSFETs (TSNWFETs) fabricated using conventional CMOS compatible process. • Transport property: • Single electron tunneling. • Conductance quantization. • Ballistic transport. • Optimum size: dNW=4nm • Volume inversion • Scattering Questions?

  8. References • Sung Dae Suk, et al., “High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication on Bulk Si Wafer, Characteristics, and Reliability,” IEDM 2005, pp. 717-720. • Kyoung Hwan Yeo, et al., “Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15nm length gate and 4nm radius nanowires,” IEDM 2006. • Keun Hwi Cho, et al., “Observation of single electron tunneling and ballistic transport in twin silicon nanowire MOSFETs (TSNWFETs) fabricated by top-down CMOS process,” IEDM 2006. • Sung Dae Suk, et al., “Investigation of nanowire size dependancy on TSNWFET,” IEDM 2007, pp. 891-894.

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