Download
r d status plan for fpccd vtx detector n.
Skip this Video
Loading SlideShow in 5 Seconds..
R&D Status/Plan for FPCCD VTX Detector PowerPoint Presentation
Download Presentation
R&D Status/Plan for FPCCD VTX Detector

R&D Status/Plan for FPCCD VTX Detector

111 Views Download Presentation
Download Presentation

R&D Status/Plan for FPCCD VTX Detector

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. R&D Status/Plan for FPCCD VTX Detector 2007/5/31 Y. Sugimoto KEK @LCWS2007

  2. FPCCD Vertex Detector • Accumulate hit signals for one train (2840 BX) and read out between trains (200ms)  Completely free from EMI • Fine pixel of ~5mm (x20 more pixels than “standard” pixels) to keep low pixel occupancy • Spatial resolution of ~1.5mm even with digital readout • Excellent two-track separation capability • Fully depleted epitaxial layer to minimize the number of hit pixels due to charge spread by diffusion • Two layers in proximity make a doublet (super layer) to minimize the wrong-tracking probability due to multiple scattering • Three doublets (6 CCD layers) make the detector (in GLD DOD) • Tracking capability with single layer using hit cluster shape can help background rejection • Multi-port readout with moderate (~10MHz) speed (Very fast readout (>50MHz) not necessary) • Simple structure  Large area • No heat source in the image area

  3. Development of Fully-depleted CCD by HPK • Confirmation of full-depletion using line-focused LASER • LASER light (532nm) focused to a thin (<pixel size) line was illuminated to CCDs slightly inclined w.r.t. CCD pixel grid Effectively scan inside a pixel • Compare signal distribution between Vgate=-7V and Vgate=+6V during LASER illumination • If distributions are same, the CCD is fully depleted in both cases Laser

  4. Potential v.s. Vgate Vgate=0 – 6 V

  5. Results Projection

  6. S7170 Standard • Back-illumination • Low resistivity epitaxial layer  thin depletion layer • S.N.; BF3-006 -7V +6V 1 pixel

  7. S7170 Deep2 • Higher resistivity 30mm thick epitaxial layer • SN; FF16-011 -7V +6V

  8. S7170 SPL 15mm • Higher resistivity 15mm thick epi-layer • SN;11-12 -7V +6V

  9. S7170 SPL 24mm • Highest resistivity 24mm thick epi-layer • SN; 22-20 -7V +6V

  10. Conclusion • Fully depleted epitaxial layer is the key issue of FPCCD vertex detector • The signal distributions of a newly developed CCD, S7170-0909 SPL 24mm, at two different gate voltages of -7V and +6V during the LASER illumination were same • From this result, we can conclude that S7170-0909 SPL 24mm is fully depleted even at the gate voltage of -7V • Measurement of Lorentz angle and study of radiation hardness of this CCD are planned in this FY • Fabrication of smaller pixel, multi-port readout CCD and ASIC for readout of the multi-port CCD are also planned in this FY