On Sub-optimality and Scalability of Logic Synthesis Tools

1. On Sub-optimality and Scalability of Logic Synthesis Tools Igor L. Markov and Jarrod A. Roy Dept. of EECS, University of Michigan at Ann Arbor

2. Outline • Motivation and Previous Work • Results on Common Problems • Primality Testing as a Benchmark • Theoretical Bounds • Empirical Results • Polynomial Fitting • Conclusions and Further Work

3. Quantifyng Scalability • Previous work has been in physical design • L. Hagen, J.H.Huang, and A.B.Kahng,“Quantified Suboptimality of VLSI Layout Heuristics”, DAC 1995, pp. 216-221 • Test cases with optimal cost grow linearly with problem size • C.C.Chang, J.Cong, and M.Xie, “Optimality and Scalability Study of Existing Placement Algorithms,” ASP DAC 2003, pp. 621-627 • Placement Examples with Known Optima (PEKO) - rather artificial circuits (no long wires) • Show a 2x sub-optimality in placement tools • Our interest: logic synthesis

4. Our Work • Evaluate scalability of ESPRESSO, SIS, BDS • Introduce primality testing as a scalable benchmark for synthesis tools •  poly-sized circuits; we derive an upper bound • No such poly-sized circuits actually known • Show exponential sub-optimality (pessimistic) • Multipliers not a problem – can be instantiated

5. Results on Common Tasks • Parity • ESPRESSO & SIS: circuits as big as input truth tables • BDS: circuits grow linearly • Addition • ESPRESSO & SIS: work on up to 7(8)-bit adders ~polynomial circuit growth • BDS crashes on all inputs (but not immediately) • Multiplication • ESPRESSO & SIS: work on up to 4(8)-bit multiplierssuper-polynomial circuits growth • BDS crashed on all but the 2-bit multiplier

6. Log-Log Plot for Adders Poly  Straight Line

7. Log-Log Plot of Multipliers

8. Primality Testing • AKS algorithm (Agrawal, Kayal & Saxena) “PRIMES is in P”, preprint, August 2002 http://www.cse.iitk.ac.in/news/primality.html • 1st deterministic poly-time algorithm for primality testing • Runs in O*(n12) time for n-bit integers on a RAM machine • For 1-tape Turing machine: our bound is O(n26) • Well-known result in Complexity Theory implies thatcombinational circuits of size O(n52) exist • The Sophie Germain conjecture, if true,reduces the circuit size bound to O(n24) • “True for practical purposes” (verified up to astronomic n)

9. Results • ESPRESSO-exact: runs out of steam at 19 bits • SIS (best of full_simplify & script rugged ) • Runs out of steam at 20 bits, but otherwise results no better than those for ESPRESSO • BDS: runs out of steam at 7 bits • No better than SIS or ESPRESSO • Super-linear trends in log-log plotssuggest exponential growth in circuit size

10. Log-Log Plot of Espresso Results Known Exponential

11. Log-Log Plot of SIS Results

12. Log-Log Plot of BDS Results

13. Fitting Polynomials to the data • Too few data points to see if the trend fits a 24th degree polynomial • We fit the Espresso and SIS data to smaller degree polynomials (up to 18th) • 13th-15th degree were most reasonable for Espresso • 13th-16th degree were most reasonable for SIS • Several characteristics of the fits suggest circuit size growth is exponential

14. Properties of Good Poly-Fits • Monotonically increasing • Most coefficients should be positive • Leading coefficient must be positive • Increased degree should improve fit • Behavior outside data regionshould be reasonable

15. Polynomial Fitting Espresso Data

16. Polynomial Fitting SIS Data

17. Conclusions and Further Work • Primality testing appears to expose an exponentialsub-optimality in synthesis tools • Continued work with primality testing • Try new tools: M31, etc. • Derive better bounds on circuit size • Use more sophisticated algorithms like Fast Fourier multiplication • Factor in improvements to AKS • Build primality testing circuits in a VHDL, synthesize, see how well they scale • Work beyond primality testing • Scalability studies based on doubling constructions in the spirit of Hagen et. Al.