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SRP: Architecture

SRP: Architecture. Irakli MANDJAVIDZE DAPNIA, CEA Saclay, 91191 Gif-sur-Yvette, France. Overview. SRP in ECAL Off-Detector Electronics The Selective Read-out Processor The SRP architecture The Algorithm Board. SRP in ECAL OFF-Detector Electronics. Trigger Towers. Operation

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SRP: Architecture

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  1. SRP: Architecture Irakli MANDJAVIDZE DAPNIA, CEA Saclay,91191 Gif-sur-Yvette, France Irakli.MANDJAVIDZE@cea.fr

  2. Overview • SRP in ECAL Off-Detector Electronics • The Selective Read-out Processor • The SRP architecture • The Algorithm Board Irakli.MANDJAVIDZE@cea.fr

  3. SRP in ECAL OFF-Detector Electronics Trigger Towers • Operation • Receive TT flags from TCCs • Exchange frontier TT flags among ABs • Execute SR algorithm • Deliver SR flags to DCCs Partial triggerprimitives Front-ends 108 TCC L1 Trigger L1 accept All event data Classification flags: 3bit/TT 54 CCS TCS SRP12 algorithmboards Input pipelinedelay of 6.4µs/RU TTC 54 DCC sTTS Read-out flags: 3bit/TT Selected event data HLT & DAQ Irakli.MANDJAVIDZE@cea.fr

  4. Architecture A 6U VME64x crate 12 identical Algorithm Boards 1-slot VME64x compliant four ECAL partitions Crate controller Boundary scan controller (?) Operation Receive TT flags from 108 TCCs from up to 12 TTCs per AB Exchange frontier TT flags among ABs among up to 8 ABs Execute SR algorithm Deliver SR flags to 54 DCCs to up to 6 DCCs per AB Interfaces Optical serial links for: TCC-AB and AB-DCC AB-AB A TTC interface per AB A TTS interface per partition sTTS signals of 3 ABs merged ... and sent by any of the ABs The Selective Read-out Processor Irakli.MANDJAVIDZE@cea.fr

  5. Algorithm Board under development 2 boards expected in September SRP crate SRP Architecture B S C C Leftend-cap Left½ barrel Right½ barrel Rightend-cap Rx: TCC input A B A B A B A B A B A B A B A B A B A B A B A B Tx: DCC output Parallel optic modules Rx: AB input Four Partitions Tx: AB output TTC input TTS input1 RJ45 TTS input2 TTS output Irakli.MANDJAVIDZE@cea.fr

  6. Algorithm Board ABRx ABTx DCCTx P1 J0 P2 VME buffers Power supply Xilinx V2Proxc2vp70-6-ff1704 BS controller &JTAG chain Core FPGA VMESerial linksAlgorithms FPROMs Memory Clocksynthesizer TCS interface SNAP12 MSA pluggableparallel optic modules QPLL TTCrx TTCRx RJ45 connectors Aux. connector TrueLite TTSIN TTSOUT Cons., JTAGEthernet TTSIN O/E Same hardware for AB and AB Tester Irakli.MANDJAVIDZE@cea.fr

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