1 / 21

February 6th, 2007

Update of the “Digital EMC project”. February 6th, 2007. Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS. Outline. Part I : AMIS problems on RD2E PCB and Chip Part II : di/dt measurement

kitty
Download Presentation

February 6th, 2007

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Update of the “Digital EMC project” February 6th, 2007 Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS

  2. Outline • Part I: AMIS problems on RD2E PCB and Chip • Part II: di/dt measurement • Part III: Improved EMI-Suppressing regulator structure • Part IV: Future work

  3. Part I. AMIS problem 1 – USB module USB module (with shielding box) Oscillator inside the USB module

  4. AMIS problem 2 – Internal Oscillator VDD<1> Emission Cause trouble for 1 Ohm method, Less problematic for di/dt measurement Internal Oscillator VSS

  5. Part II. di/dt measurements Setup 3 Setup 2 Setup 1 VCCC =12 V VCC = 4.5 V ~ 8 V VDD2 = 3.3 V i2 i3 i1 EMI-Suppressing Regulator (MICAS) VDD<1..10> Low Drop-out / Serial Regulator AMIS digital load VCC i5 and V2 GND i4 and V1 configuration bits PC

  6. Focus on setup-1 – Some preliminary results VDD3 (separate power supply) VDD2 = 3.3 V i1 Internal Oscillator Digital Load (Shift register output buffer) clk EMI GND

  7. 1. The impact of internal oscillator onCurrentSpectrum of VDD2 Fig. 1 Fig. 2 QP<1>=QP<48>=QP<49>=QP<51>=‘1’ Note: internal oscillator disable, di/dt on VDD2, QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: internal oscillator enable, di/dt on VDD2, Conclusion: Internal clock may cause some problems

  8. 2. Comparison of internal and external clock on CurrentSpectrum of VDD2 Fig. 2 Fig. 3 QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: internal oscillator enable, di/dt on VDD2, QP<1>=QP<48>=QP<51>=‘1’, QP<49>=‘0’, QP<50>=‘0’, Note: external clock enable, di/dt on VDD2, internal oscillator is powered down Conclusion: Much worse with external clk

  9. 3. The impact of oscillator inside USB module on CurrentSpectrum of VDD2(no switching activity) Fig. 2 Fig. 4 QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: internal oscillator enable, di/dt on VDD2, QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: di/dt on VDD2, USB module is powered down and the latch is enabled No big difference

  10. 4. The impact of internal oscillator in USB module on CurrentSpectrum of VDD2(working condition) Fig. 5 Fig. 6 QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’ QP<53>=‘1’, Note: di/dt on VDD2, USB module is powered down and the latch is enabled QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’ QP<53>=‘1’, Note: di/dt on VDD2, No big difference

  11. 5. The impact of load on CurrentSpectrum of VDD2 • 4.02 MHz clk from internal oscillator, • Data input from on-chip 21-bit Random Generator. only clock present 1 DFF chain 2 DFF chains 5 DFF chains 4 DFF chains 3 DFF chains

  12. 6. The impact of load on CurrentTransient of VDD2 3 DFF chains 1 DFF chain 2 DFF chains Pk-Pk: 66.3mV Pk-Pk: 45mV Pk-Pk: 23.8mV 5 DFF chains 4 DFF chains Pk-Pk: 108.1mV Pk-Pk: 86.9mV

  13. 7. The impact of load on di/dtTransient of VDD2 In general, as more DFF chains are on, the di/dt peak increases proportionally.

  14. Conclusions • On-chip internal oscillator won’t hurt much, which is common for all measurements. • Oscillator inside USB module is not a problem at all, shielding box can do most of the job. • Setup for massive measurements is in preparation • Automatic setup shall be ok by this week, • Agreement on data to be measured ?

  15. Part III: EMI-Suppressing Regulator possible improvement z1 cancel off the p1 Make the p2 cut-off frequency This zero is intrinsic for this feedback topology sacrifices dynamic noise performance peaking H(s)-dB p2 z1 p1 Frequency Previous structure problem: di/dt TF: pole-zero tracking !!

  16. Cascode compensation (Ahuja, JSSC 12/1983) The feed forward path is removed, Miller effect still available, A2 Cc instead of (1+ A2 Cc ) for miller cap, Improved PSRR performance, 2 1

  17. Ahuja inspired... However, our di/dt TF is other way around !!! According to maple simulation, things are getting even worse because the -3dB frequency is shifted to even high frequency. The reason is that there is voltage gain from V3 to Vctrl, i.e.: Vctrl /V3=gm2*Rota This trick doesn’t help If gm2*Rota << 1 ? Kill the Vctrl/V3 gain ! !!! One degree of freedom is added !!!

  18. Some formulas • p1 : • p2 : • z1: Now (Assume: ) • p1 : • p2 : • z1: Previous

  19. Maple calculation of the new structure -3dB frequency moves down to below 40 kHz, At 100 kHz, there is already decent di/dt suppression. -3dB Maple calculation is ready 100 kHz • To Be Done: • Spice simulation to verify Maple calculation ? • Re-design EMI-Suppressing Regulator based on this new structure ?

  20. Part IV: Future Work • Continue the digital load measurements, • More analysis for new structure: • Stability and Transient, • Spice simulation.

  21. Questions Thank you for your attention

More Related