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Introductory Computer Organization The Microarchitecture Level Tannenbaum 4.1.1, 4.1.2, 4.1.3. Shannon Tauro / Jerry Lebowitz. MicroArchitecture Level. MicroArchitecture Level Job is to implement the Instruction Set Architecture (ISA). Big Picture. Instruction Set Architecture (ISA).

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Introductory Computer OrganizationTheMicroarchitecture LevelTannenbaum 4.1.1, 4.1.2, 4.1.3

  • Shannon Tauro/Jerry Lebowitz


Microarchitecture level
MicroArchitecture Level

  • MicroArchitecture Level

    • Job is to implement the Instruction Set Architecture (ISA)



Instruction set architecture isa
Instruction Set Architecture (ISA)

  • Depends on ISA being implemented

    • Reduced Instruction Set Computing (RISC)

    • Complex Instruction Set Computing (CISC)


Reduced instruction set computing risc
Reduced Instruction Set Computing (RISC)

  • Strategy based on the insight that simplified (as opposed to complex) instructions can provide higher performance if this simplicity enables much faster execution of each instruction

  • Small, highly-optimized set of instructions

  • Used in SPARC, Power PC

  • ARM architecture processors in smart phone and tablets are based on RISC


Complex instruction set computing cisc
Complex Instruction Set Computing (CISC)

  • Where single instruction can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single instructions

  • Used in Pentium, Core i7 processors


Design of microarchitecture
Design of Microarchitecture

  • Want to:

    Explain general principles of micro-architecture design but

    THERE ARE NONE!! EACH IS UNIQUE


Example microarchitecture
Example MicroArchitecture

  • A subset Java Virtual Machine (JVM) for integer operations will be discussed

    • IJVM : Integer Java Virtual Machine

  • Our microarchitecture will contain a microprogram (in ROM) whose job is to:

    • Fetch

    • Decode

    • Execute

      IJVM instructions


  • IJVM

    • Each instruction at the ISA level is a function that is called by a master program

    • Imagine the design of MicroArchitecture as the following code:

    • The microprogram has a set of variables

      • Values represent the STATE of the computer


    Example microarchitecture1
    Example MicroArchitecture

    • IJVM Instructions: short; usually 1-2 fields

    • Every ISA instruction has an opcode

    • Many ISA instructions have operands

    • Model of Execution:

      fetch-decode-execute cycle

      Micro-instructions form the microprogram


    CPU

    CPU = Controller + Datapath

    • Datapath: contains

      • ALU

      • Registers

      • Inputs & outputs (not shown)


    Ijvm datapath

    Registers are only addressable at the microcode level

    IJVM Datapath

    MDR – memory data register

    MAR – memory address register

    MBR – memory buffer register – holds the instruction stream as it comes in from memory

    CPP – Constant pool pointer

    LV – Pointer to Local variables

    SP – Pointer to the top of the stack

    TOS – Contains the value of the memory location pointed to by SP

    OPC – Temporary register

    • Datapath: contains

      • 32-bit registers

        • Registers are accessible only by micro-program at the microArchitecture level

      • B-BUS: Contains the contents of registers

      • C-BUS: Contains the output of ALU

        • Can write to multiple registers at once


    Controlling registers
    Controlling Registers

    • Each of these registers are controlled by two signals

    • A solid arrow under a register indicates a control signal that writes (loads) the register from the C bus

    • An open arrow under a register indicates a control signal that enables the register’s output onto the B bus

    • To initiate a memory read or write, the appropriate memory register must be loaded, then a read or write signal issued to the memory


    Ijvm datapath1
    IJVM Datapath

    • Datapath: contains an ALU:

      • Needs 2 inputs:

        A(left) register H (1 source)

        B(right) Bus B (9 sources)


    Ijvm arithmetic logic unit
    IJVM Arithmetic Logic Unit

    F0 and F1 used to determine the ALU operation

    ENA and ENB for individually enabling inputs

    INVA for inverting the left input

    INC forcing a carry into the low order bit (add 1 to the result)

    ALU Truth Table

    • ALU Operation:

      • To load H:

        • Choose an ALU function that

        • Passes the value at the B input through the ALU

        • Writes value back into H

          i.e. identity of B

    Sample inputs

    6 ALU control lines


    Ijvm arithmetic logic unit1
    IJVM Arithmetic Logic Unit

    • ALU Operation:

      • Read and write in same cycle

        • Can happen with magic and timing

          1st half of cycle one reads register

          2nd half one can write

    ALU Truth Table


    Memory operations
    Memory Operations

    • Two ways to address memory

      • 32-bit word-addressable memory

        • Memory Address Register (MAR)

        • Memory Data Register (MDR)

    • The 8-bit byte-addressable port is controlled by the PC

      • Reads 1 byte into the low-order memory of the memory buffer register (MBR)- (read only port)


    Registers
    Registers

    • MAR contains word addresses

      • 0,1,2,… refer to consecutive words

    • MAR/MDR: used to read/write ISA-level data words

    • PC contains byte addresses

      • 0,1,2,… refer to consecutive bytes

    • PC/MBR: used to read the executable ISA-level program (consists of a byte stream)


    Microinstructions
    MicroInstructions

    • ALU, registers, buses

      • All have control signals

    • IJVM data path

      • 29 signals are needed for one cycle of the data path

      • A cycle consists of gating values out of registers onto the B bus, propagating signals through the ALU and driving them on the C bus, and writing the results in the appropriate registers

    These signals together create the

    Binary Micro-Instruction


    Signals
    Signals

    • Signals are divided up into 5 functional groups

      • 9 signals to control writing data from the C bus into registers

      • 9 signals to control enabling registers onto the B bus for ALU input

      • 8 signals to control the ALU and shifter functions

      • 2 signals (not shown) to indicate memory read/write via MAR/MDR

      • 1 signal (not shown) to indicate memory fetch via PC/MBR


    Memory read operation
    Memory Read Operation

    • 1st Bus Cycle:

      • Memory address is loaded into memory Address Register (MAR)

    • 2nd Bus Cycle:

      • Data is fetched from memory and stored in registers

    • 3rd Bus Cycle:

      • Data can now be used in an instruction

    • Note:

      • One can start another instruction during the 2nd bus cycle

        • One that does not need information from the previous read


    Microinstruction format
    MicroInstruction Format

    • 36-signals correspond to one IJVM instruction


    Microinstruction format groups
    MicroInstruction Format Groups

    Addr: Contains the address of a potential next microinstruction

    JAM: Determines how next microinstruction is selected


    Microinstruction format groups1
    MicroInstruction Format Groups

    • ALU: controls the ALU & shifter functions

      C: Selects which registers are written from the C Bus

      Mem: Memory Functions

      B: Selects the B bus source


    Finally
    Finally….

    • Here we are!!! Our Controller + Data path!!! 


    4 16 decoder
    4-16 Decoder

    • Decoder is a device which does the reverse operation of an encoder

      • Multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs

      • Converts the bits stored in the microinstruction – into the control signals that control the other parts of the CPU

    • 4 inputs -> 16 outputs


    Sequencer
    Sequencer

    • Responsible for stepping through the sequence of operations necessary for execution of a single ISA instruction

    • Produces two kinds of information on each cycle

      • State of every control signal in the system

      • Address of the microinstruction that is to be executed next


    Control store rom
    Control Store (ROM)

    • Can be implemented as a memory that holds the microprogram (memory cells) or logic gates


    Control store

    Needs its own memory address register and memory data register (MPC) and MIR

    Doesn’t need read and write signals since it is continuously being read

    Control Store

    • Accessed through MBR and MDR

    • Holds microinstructions (not ISA instructions)

    • Properties:

      • 512 words

      • 1 word = 36-bit micro-instruction

    • Has it’s own address register: MicroProgram Counter (MPC)

    • Has it’s own data register: MicroInstruction Register (MIR)


    Important difference
    Important Difference…. register (MPC) and MIR

    • Main Memory:

      • Program Instructions; executed sequentially (except for branches) :

        • Incrementing the PC means execute the next instruction

    • Control Memory:

      • Each microinstruction explicitly specifies its successor

      • It is a Read Only Memory


    Micro program responsibilities
    Micro Program Responsibilities register (MPC) and MIR

    • The microprogram needs to:

      • Drive the datapath

      • Determine which instruction to execute next


    Micro program responsibilities1
    Micro Program Responsibilities register (MPC) and MIR

    • To determine the next instruction…

    • Begins after MIR has been loaded and is stable

    • 1a) 8-bit next address field is copied to MPC

    • 1b) Inspect JAM field:

    • if 000 

    • do nothing, next instruction is initialized

    • if !(000) test JAMN & JAMZ

    • if (JAMN = 1 || JAMZ = 1)

    • 1-bit N and/or Z flip-flip is ORed

    • into high-order bit of MPC

    • MPC = (Value of Next Address)

    • or

    • (value of next address with high order bit OR-ed with 1)

    • Allows one to branch to another instruction


    Simulation after mir is stable
    Simulation… register (MPC) and MIRAfter MIR is stable

    Apply High Bit

    Result to MPC

    1a

    1b

    Test n & z


    An example isa stack based machine
    An Example ISA - register (MPC) and MIRStack Based Machine

    • Stack Based Machine: Operands are placed on a stack and the result is stored on the stack

    • SP: top of stack pointer

    • LV: pointer to local variables

    • The data structure between LV and SP is called a local variable frame


    Method calls variables
    Method Calls (Variables) register (MPC) and MIR

    Stored on a stack

    (b and c returns)

    LV

    LV

    LV

    LV

    a3

    b3

    b3

    d3

    a3

    c3

    a3

    d6

    a3

    SP

    SP

    SP

    SP

    c2

    a2

    a2

    a2

    d5

    b2

    b2

    a2

    d2

    a1

    d1

    a1

    a1

    a1

    b1

    c1

    d4

    b1

    a

    b

    c

    d


    Method calls operands
    Method Calls register (MPC) and MIR(Operands)

    Stored on a stack

    • Want a1 = a2 + a3

      • Push a2 and a3 on the stack

      • Pop a2 and a3, add them together and push the result on the stack

      • Pop the result and store it in a1

    Note: Variables and operand can be intermixed on the stack


    Ijvm memory
    IJVM Memory register (MPC) and MIR

    • Constant pool

      • Constants, strings, pointers to other area of memory (cannot be changed during execution)

      • Cannot be written to a IJVM program

    • Local variable frame

      • Used when methods are called (storing variable)

    • Operand stack

      • Part of the local variable frame

    • Method area

      • Where the program resides

    • Size

      • 4,294,967,296 bytes (4 GB)


    Ijvm instruction set
    IJVM Instruction Set register (MPC) and MIR

    Each instruction consists of an opcode and sometimes and operand


    Ijvm instruction examples
    IJVM Instruction Examples register (MPC) and MIR

    • Push a word on a stack

      • LDC_W, ILOAD, BIPUSH

    • Pop off a stack

      • ISTORE, BOPUSH

    • Arithmetic

      • IADD, ISUB

    • Boolean

      • IAND, IOR

    • Branching

      • GOTO, IFEQ, IFLT, IF_ICMPEQ


    Compiling java to ijvm
    Compiling Java to IJVM register (MPC) and MIR

    corresponding

    corresponding

    Java Code

    IJVM assembly language

    Binary program


    Compiling java to ijvm1
    Compiling Java to IJVM register (MPC) and MIR

    • First j and k are pushed onto the stack, added, and result is stored in i

    • Then i and the constant 3 are pushed on the stack and compared

      • If equal, branch to L1 where k is set to 0

      • If not equal, the compare fails and the code following the IF_ICMPEQ is executed

        • When done, branch to L2


    Stack progression
    Stack Progression register (MPC) and MIR

    k

    j

    j

    j+k

    0

    1

    2

    3

    4

    1

    3

    i

    i

    j

    j

    5

    6

    7

    8

    9

    j - 1

    0

    14

    10

    11

    12

    13

    15


    Implementation needed
    Implementation needed register (MPC) and MIR

    • MicroArchitecture has been defined now we need to define an implementation


    An example implementation
    An Example Implementation register (MPC) and MIR

    • Define a High-Level Micro Assembly Language (MAL)

      • Tailored to be consistent with the microArchitecture that was just defined

    • Simple assignment statements will be used to indicate operations

    • To copy something from SP to MDR

      • MDR = SP

    • To indicate the use of the ALU functions other than passing through the B bus

      • MDR = H + SP (add the contents of the H register to SP and writes the result into the MDR)


    High level micro instructions
    High-level micro-Instructions register (MPC) and MIR


    Valid high level instructions
    Valid High-level Instructions register (MPC) and MIR

    • Need to define only valid operations

    • Valid sources are MDR, PC, MBR, MBRU (unsigned version of the MBR), SP, LV, CP, TOS, OPC

      • Act as sources to the ALU on the B bus

    • Valid destinations are MAR, MDR, PC, SP, LV, CPP, TOS, OPC, or H

      • Act as destinations for the ALU output on the C bus

    • The statement MDR = SP + MDR is illegal because the addition (other than increment or decrement) must involve the H register

    • The statement H = H - MDR is illegal because the only possible source of the subtrahend (the value being subtracted) is the H register


    High level instructions
    High-level Instructions register (MPC) and MIR

    • There are only 112 valid microinstructions

      • Three columns

        • Symbolic label

        • Actual microcode

        • Comment

    • Note that consecutive microinstructions are not necessarily located in consecutive memory locations in the control store


    Valid statements 1
    Valid Statements (1) register (MPC) and MIR




    The language to be implemented

    High Level Instructions register (MPC) and MIR

    The Language to be Implemented

    IJVM: ISA Instructions

    Compiler/

    Assembler

    Each ISA instruction is represented as several micro-code instructions

    MicroProgram

    in CPU

    Micro-Instructions


    Ijvm microprogram
    IJVM Microprogram register (MPC) and MIR

    • Has a main loop that fetches – decodes – executes (IJVM instructions)

      • Begins on the label Main1

      • PC needs to be continually updated to contain the address of the next instruction

      • Opcodes need to be fetched into the MBR


    Interpreter
    Interpreter register (MPC) and MIR

    • Assume the MBR contains the value 0x60 (IADD)

    • In one micro-instruction

      • Increments the PC leaving it containing the address of the first byte after the opcode

      • Initiates the fetch of the next byte into the MBR

      • Performs a multiway branch to the address in the MBR. This address is equal to the numerical value of the opcode being executed


    • Backup register (MPC) and MIR


    Datapath timing
    Datapath Timing register (MPC) and MIR

    • Propagation Delay

      • Just as in our homework problem, there is a delay before the output of our gates is stable

    • Δx before values is stable; then ALU & shifter can begin computation

    • Δy: ALU & Shifter outputs are stable

    • Δz: results propagated along C bus to registers

    • Rising Edge: Registers Latch values into memory cells

    • Falling Edge:

      • signals set up for output

      • Δw time passes before valid


    Datapath timing1
    Datapath Timing register (MPC) and MIR

    • Propagation Delay

      • Just as in our homework problem, there is a delay before the output of our gates is stable

    • Δy: ALU & Shifter outputs are stable

    • Δz: results propagated along C bus to registers

    • Rising Edge: Registers Latch values into memory cells

    Δx before values is stable

    then ALU & shifter can begin computation


    Datapath timing2
    Datapath Timing register (MPC) and MIR

    • Propagation Delay

      • Just as in our homework problem, there is a delay before the output of our gates is stable

    • Δz: results propagated along C bus to registers

    • Rising Edge: Registers Latch values into memory cells

    Δy: ALU & Shifter outputs are stable


    Datapath timing3
    Datapath Timing register (MPC) and MIR

    • Propagation Delay

      • Just as in our homework problem, there is a delay before the output of our gates is stable

    • Δz: results propagated along C bus to registers

    • Rising Edge: Registers Latch values into memory cells

    • Δz:

      results propagated along C bus to

      registers


    Datapath timing4
    Datapath Timing register (MPC) and MIR

    • Propagation Delay

      • Just as in our homework problem, there is a delay before the output of our gates is stable

    Rising Edge: Registers Latch values into memory cells


    Datapath timing5
    Datapath Timing register (MPC) and MIR

    • To Implement this requires:

      • Rigid timing

      • Long clock cycle

      • Know minimum propagation delay

      • Fast load of registers from C Bus


    Datapath timing6
    Datapath Timing register (MPC) and MIR

    • Things to Note:

      • Falling Edge Signals Start of Bus Cycle

      • Rising Edge Signals End of Bus Cycle

      • All units are operating all the time. The values are garbage until the known delay has passed.

    • Clock Length >= Δw + Δx + Δy + Δz


    Microinstruction format groups2
    MicroInstruction register (MPC) and MIR Format Groups

    • JAM: Determines how next microinstruction is selected

      N: ALU result was negative

      A-B= -ive A < B

      Z: ALU result was zero

      A-B = 0  A = B


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