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Verification Methodology Based on Algorithmic State Machines and Cycle-Accurate Contract Specifications. Sergey Frenkel 1 and Alexander Kamkin 2 1 Institute of Informatics Problems of the Russian Academy of Sciences 30/6, Vavilov Street, Moscow, 117900, Russia E-mail: email@example.com
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Sergey Frenkel1 and Alexander Kamkin2
1Institute of Informatics Problems of the Russian Academy of Sciences
30/6, Vavilov Street, Moscow, 117900, Russia
2Institute for System Programming of the Russian Academy of Sciences
25, A. Solzhenitsyn Street, Moscow, 109004, Russia
Currently above DESIGN PROCESS are implemented in the following steps:
Input: behavioral description, usually by some Hardware Design Languages (HDL, e.g.,Verilog, VHDL), or by a system ones (e.g.,Csystem, some Petri net based languages, etc).
Output: generated architecture for design at RTL, namely:
data path (interconnection of adders, multipliers, etc),
FSM model of control unit (signals to control data path), scheduling and binding
Input: RTL description (HDL).
converts into network of logic primitives (depending on design style).
Physical Design: Out of our consideration
Our tool can provide the input for logic synthesis (in CADENCE, SYNOPSIS, MENTOR GRAPHIC) automatically.
One of important contributions of our proposal could be a new bridge between Architectural (System) synthesis and Logic one, also taking into account some requirements to Fault-tolerant design.
50-80% of ASIC / IP / SoC design effort goes to verification, whathas effects on Schedule, Cost, Quality.
Due to chip complexity this becomes more and more difficult, namely:
A work of a designer is resulted in two or three activities and human/equipment resources which have been spent for one of them should be kept back in another.
Validation ~ Verification
Verification via Simulation
Application Specific Languages
Verilog, VHDL, Cycle-Accurate Contract Specification Language
propagates sets of states, not individual trajectories
PROPERTY IS TRUE OR A COUNTER EXAMPLE
An Algorithmic State Machine (ASM) is the directed connected graph containing an initial vertex (Begin), a final vertex (End) and a finite set of operators and conditional vertices.
The operators and conditional vertices have only one input, the initial vertex has no input. Initial and operator vertices have only one output, a conditional vertex has two outputs marked by "1“ and "0". A final vertex has no outputs. Each operator include some body in a pseudocode, and its execution takes a clock of the target system time
The following are the major steps in the ASM methodology:
If followed correctly, the ASM method produces a hardware design in a systematic and logical manner
Let us an operator Yb be implemented. The sequence of the actions after Yb can be represented by ASM as following:
The operator Y3 is executed after Yb when x1x4x3=1,Y1 is executed afterYb when x1x’3=1,
Y5 is excuted after Yb when x1x4x’3=1 or x’1=1, that is:
Yb→ x1x4x3Y3 + x1x4x'3Y5+ x1x'4Y1+ x'1Y5
Translated ASM model is converted automatically in VHDL/VERILOG test bench of a behavior model of the target system, which is simulated by a well known tool, e.g. by ModelSim (Mentor Graphic).
The detected output is the desirable behavior of the target system which should compare with the result of the structural synthesis , implemented by ABELITE (“Actual output”).This actual output is also the result of simulation by the same tool, e.g. ModelSim.
Conditinos of Natural Ordering of Counting
SPEC AG (((bit0=0)&(bit1=1) &(bit2=0)) ->AX((bit0=1)&(bit1=1)&(bit2=0)))
SPEC AG (((bit0=0)&(bit1=1) &(bit2=0)) ->AX((bit0=1)&(bit1=1)&(bit2=1)))