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Instruction Set Architecture (ISA) for Low Power

Instruction Set Architecture (ISA) for Low Power. Hillary Grimes III Department of Electrical and Computer Engineering Auburn University. Outline. Introduction ISA Characteristics ISA Design CISC vs. RISC Register File Size Instruction Word Length Code Compression

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Instruction Set Architecture (ISA) for Low Power

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  1. Instruction Set Architecture (ISA) for Low Power Hillary Grimes III Department of Electrical and Computer Engineering Auburn University

  2. Outline • Introduction • ISA Characteristics • ISA Design • CISC vs. RISC • Register File Size • Instruction Word Length • Code Compression • Examples: ARM, Thumb, & Thumb-2 Instruction Sets • Proposed ISA Design for Low Power • Future Work • Resources

  3. ISA Characteristics • Three main characteristics: • Register Organization • # of registers & their sizes • Memory Organization • Address space - # of memory locations • Addressablity - # of bits stored @ each location • Instruction Set • List of opcodes – defines instructions supported • Addressing modes – defines how operand values are obtained • Instruction Formats – binary format for encoding instructions

  4. ISA Design • Typically, an ISA is designed for performance  Power consumption is often ignored • ISAs designed for performance only are generally “power hungry” • User-Level instructions perform many operations that dominate total power dissipation • For low power applications, such as embedded systems, we would like to design an ISA that lowers power dissipation without a significant reduction in performance

  5. CISC vs. RISC • CISC • Less instructions executed than in RISC (higher code density) • Reduced energy consumed fetching instructions • RISC • More instructions than CISC, therefore more energy consumed fetching instructions • Data & control paths are typically simpler, therefore less energy consumed per instruction

  6. Register File Size • Small # of general purpose registers • Smaller Register File Size • less energy consumed per register file access • More operands fetched from memory • more energy consumed by memory accesses • Large # of general purpose registers • Large Register File Size • more energy consumed per register file access • Less operands fetched from memory • less energy consumed by memory accesses

  7. Instruction Word Length • Required memory address space cannot be reduced, and usually determines register width. • Many embedded processors use 32 bit instruction words. • Reducing instruction width to 16 bits requires reformatting for a 32 bit external bus to fill the memory address space requirement. • Reduces energy consumed by each instruction fetch (by up to 50%) • Also reduces performance by the need to reformat for a 32 bit external bus

  8. Instruction Word Length • When the energy consumed by external memory accesses dominates the total energy consumption, energy efficiency may be significantly improved • True for small on chip caches (<8kb) • Not true for larger on chip caches (16kb or larger). (Not as much energy saved)

  9. Code Compression • Reducing the amount of space required for porgram code reduces the amount of memory that must be fetched for program execution. • This reduces the total power consumed by overall instruction fetches • Two ISAs developed for the ARM processor family that utilize code compression: • Thumb • Thumb-2

  10. Thumb Instruction Set • The Thumb instruction set is a subset of 16-bit instructions implemented over the initial 32-bit ARM instruction set • Thumb code can have a higher density than most CISC processors, but the Thumb set is more limited than the 32-bit ARM Instruction set • ARM instructions can be conditionally executed, but Thumb instructions are always executed • The ARM set consists of 3-address instructions, but the Thumb set contains many 2-address instructions

  11. Thumb Instruction Set • Switching between the ARM set & the Thumb set is done at runtime • Mode switching between ARM & Thumb causes a reduction in performance • When using the Thumb set, the fetched 16-bit instruction is decoded to a 32-bit instruction & executed • Thumb code requires only 70% of the space of ARM code • Thumb code uses 30% less external memory power than ARM code

  12. Thumb-2 Instruction Set • Combines 16 & 32-bit instructions in a single instruction set • 16 & 32-bit instructions can be mixed without mode switching • Thumb-2 code size is approximately equal to Thumb code size • Thumb-2 performance is approximately the same as ARM • No performance reduction due to mode switching

  13. ARM, Thumb, & Thumb-2 Comparison Performance

  14. ARM, Thumb, & Thumb-2 Comparison Compiled Code Size • Energy efficient solution  Thumb-2 consumes less energy than ARM from instruction fetches, while keeping the same performance as ARM

  15. Proposed ISA for low Power • Idea behind proposed ISA: • Code compression similar to, but beyond Thumb or Thumb-2 • Further reduce code space containing simple accumulator based functions requiring only 1 operand • A more compressed code space means lower power consumed by external memory, and hopefully lower overall power

  16. Proposed ISA for low Power • Dual instruction sets with mode switching scheme  similar to Thumb • Uncompressed Instruction Set • Consists of both 16 & 32 bit instructions without the need for mode switching • Similar to Thumb-2 • Compressed Instruction Set • Subset of 8-bit, 1-address functions • Functionality limited to simple, non-conditional accumulator based functions • Memory accesses of 8, 16, & 32 bit widths would have to be supported, along with mode switching, possibly increasing power or decreasing performance

  17. Future Work • Future work involves answering the following questions: • Can code density be significantly increased by reducing the code space required for simple accumulator based functions? • If so, will the total power be reduced? • Will processor performance be “wiped out”? • What are the power requirements demanded by supporting memory accesses of 8, 16, & 32 bit widths? • Would these power requirements surpass the power saved? • Would this extra support have a significant impact on performance?

  18. Future Work • How would software design be affected (compilers, schedulers, etc.)? • What other support would be needed? • In general  Would this be a realistic energy efficient solution for a low power ISA?

  19. Resources • S. J. Patel, W-M. W. Hwu, and Y. N. Patt, Instruction Set Architectures, In General, 2002 • Bill Moyer, Low-Power Design for Embedded Processors, Proceedings of the IEEE, vol. 89, no. 11, 2001 • Flavius Gruian, Microprocessors: Low Power and Low EnergySolutions, Paper for the Advanced Issues in Computer Architectures course, 1999. • T.D. Burd and R.A. Brodersen, Energy Efficient Microprocessor Design, Boston: Kluwer Academic Publishers, 2002. • http://www.advantech.com/ePlatform/RISC/01.asp • http://www.egr.msu.edu/classes/ece482/Teams/97fall/xdesign2/web/technical_report.html • http://www.embedded.com/showArticle.jhtml?articleID=17701289 • http://www.embedded.com/shared/printableArticle.jhtml?articleID=15200241

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