Computer Organization and Design Memories and State Machines

1. Computer Organization and DesignMemories and State Machines Montek Singh Mon, Nov 12, 2012 Lecture 15

2. Topics • Memory Arrays • Transparent Latches • Edge-triggered Registers • Finite State Machines

3. Memory as a Lookup Table • A multiplexer to implement a lookup table: • Remember that, in theory, we can build any 1-output combinational logic block with multiplexers • For an N-input function we need a 2N input multiplexer • BIG Multiplexers? • How about 10-input function? 20-input? A B MUX Logic Fn(A,B)

4. A Mux’s Guts I 0 0 I 0 1 I 1 0 I 1 1 Decoder Selector Multiplexerscan be partitionedinto two sections. A DECODER thatidentifies thedesired input,and a SELECTOR that enables that inputonto the output. A 0 B A decodergeneratesall possibleproductterms fora set ofinputs A 1 Y B A 2 B A 3 B Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs

5. A New Combinational Device D1 • DECODER: • k SELECT inputs, • N = 2k DATA OUTPUTs. • Selected Dj HIGH; all others LOW. D2 Have Imentionedthat HIGHis a synonym for ‘1’ andLOW meansthe sameas ‘0’ DN k NOW, we are well on our way to building a general purpose table-lookup device. We can build a 2-dimensional ARRAY of decoders and selectors as follows ...

6. Shared Decoding Logic We can build a general purpose “table-lookup” device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device

7. Logic According to ROMs • ROMs ignore the structure of combinational functions ... • Size, layout, and design are independent of function • Any Truth table can be “programmed” by minor reconfiguration: • Metal layer (masked ROMs) • Fuses (Field-programmable PROMs) • Charge on floating gates (EPROMs) • ... etc. • Model: LOOK UP value of function in truth table... • Inputs: “ADDRESS” of a T.T. entry • ROM SIZE = # TT entries... • ... for an N-input boolean function, size = __________ 2N x #outputs

8. Analog Storage: Using Capacitors VREF • We’ve chosen to encode information using voltages and we know from physics that we can “store” a voltage as “charge” on a capacitor • Pros: • compact! • Cons: • it leaks!  refresh • complex interface • reading a bit, destroys it • (you have to rewrite the value after each read) • it’s NOT a digital circuit word line N-channel FET serves as an access switch bit line To write: Drive bit line, turn on access fet, force storage cap to new voltageTo read: precharge bit line, turn on access fet, detect (small) change in bit line voltage This storage circuit is the basis for commodity DRAMs

9. A “Digital” Storage Element Here’s a feedback path,so it’s no longer acombinational circuit. “state” signal appears as both input and output G 0 0 1 1 D -- -- 0 1 QIN 0 1 -- -- QOUT 0 1 0 1 Q D G • It’s also easy to build a settable DIGITAL storage element (called a latch) using a MUX and FEEDBACK: A 0 Y Q stable B 1 Q follows D S

10. Static D Latch D D Q Q G G 1 D Q 0 G Positive latch Negative latch What is thedifference? Q follows D D G Q Q stable “static” means latch will hold data (i.e., value of Q) while G is inactive, however long that may be.

11. Latch Timing >tPULSE >tSETUP >tHOLD tPULSE (minimum pulse width): guarantee G is active for long enough for latch to capture data tSETUP (setup time): guarantee that D value has propagated through feedback path before latch becomes opaque tHOLD (hold time): guarantee latch is opaque and Q is stable before allowing D to change again • Circuits with memory must follow some rules • Guarantee that inputs to sequential devices are valid and stable during periods when they may influence state changes • This is assured with additional timing specifications G D

12. Flakey Control Systems Here’s a strategy for saving 2 bucks the next time you find yourself at a toll booth!

13. Flakey Control Systems Here’s a strategy for saving 2 bucks the next time you find yourself at a toll booth!

14. Flakey Control Systems Here’s a strategy for saving 2 bucks the next time you find yourself at a toll booth! WARNING: Professional Drivers Used! DON’T try this At home!

15. Escapement Strategy The Solution: Add two gates and only open one at a time.

16. Escapement Strategy The Solution: Add two gates and only open one at a time.

17. Escapement Strategy The Solution: Add two gates and only open one at a time.

18. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

19. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

20. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

21. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

22. Escapement Strategy The Solution: Add two gates and only open one at a time.

23. Escapement Strategy The Solution: Add two gates and only open one at a time.

24. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

25. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

26. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

27. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

28. Escapement Strategy The Solution: Add two gates and only open one at a time.

29. Escapement Strategy The Solution: Add two gates and only open one at a time.

30. Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks) Key Idea: At no time is there an open path through both gates…

31. Edge-triggered Flip Flop D Q D Q D Q G G • Logical “escapement”: • Double-gated toll booth built using logic gates • Observations: • only one latch “transparent” at any time: • master closed when slave is open (CLK is high) • slave closed when master is open (CLK is low) • no combinational path all the way through flip flop • Q only changes shortly after 0 1 transition of CLK, so flip flop appears to be “triggered” by rising edge of CLK D Q D Q master slave CLK CLK Transitions mark instants, not intervals

32. Flip Flop Waveforms D Q D Q D Q G G D Q D Q master slave CLK CLK D CLK Q master closed slave open slave closed master open

33. Flip Flop Timing <tPD >tSETUP >tHOLD • tSETUP: setup time • guarantee that D has propagated through feedback path before master closes D Q • tHOLD: hold time • guarantee master is closed and data is stable before allowing D to change D Q Q CLK CLK D tPD: maximum propagation delay, CLK Q

34. Synchronous Systems Designing digital systems using a clock We will first design the main building blocks of a MIPS processor, then put it all together!

35. Synchronous Systems Combinational logic Flipflop Flipflop data trailing edge Clock leading edge On the leading edge of the clock, the input of a flipflop is transferred to the output and held. We must be sure the output of the combinational logic has settled before the next leading clock edge. Clock period must be “long enough” Clock Period >= tFF + tlogic + tsetup

36. Fetching Sequential Instructions + 4 32 32 32 32 P C Read Address Instruction flipflop Instruction Memory How about branches, etc.?

37. Datapath for R-type Instructions ALU Operation 3 5 Inst Bits 25-21 Read Reg. 1 (rs) 32 data 1 5 Inst Bits 20-16 Read Reg. 2 (rt) 5 Inst Bits 15-11 Write Reg. (rd) 32 data 2 32 Write Data RegWrite

38. Inside there is a 32 way MUX per bit Read Reg 1 5 Register 0 32 to1 MUX Register 1 Register 2 Data 1 Register 3 Register 4 Register ... LOT’S OF CONNECTIONS! Register 30 Register 31 And this is just one port! Remember, there’s data1 and data2 coming out of the register file! For EACH bit in the 32 bit register

39. Our Register File has 3 ports This is one reason we have only a small number of registers 2 Read Ports What’s another reason? 5 Inst Bits 25-21 Read Reg. 1 32 data 1 5 Inst Bits 20-16 Read Reg. 2 5 Inst Bits 15-11 Write Reg. 32 data 2 32 Write Data REALLY LOTS OF CONNECTIONS! 1 Write Port RegWrite

40. Finite State Machines • What is a State Machine? • Remember automata? • It is defined by the following: • Set of STATES • Set of INPUTS • Set of OUTPUTS • A mapping from (STATES, INPUTS) to … … the next STATE and an OUTPUT • STATE represents memory!

41. Implementing an FSM Function (comb. logic) Outputs Inputs State(flipflops) Clock

42. Summary • Regular Arrays can be used to implement arbitrary logic functions • Memories • ROMs are HARDWIRED memories • RAMs include storage elements that are read-write • dynamic memory: compact, only reliable short-term • static memory: controlled use of positive feedback • For static storage: • Level-sensitive D-latches; edge-triggered flipflops • Timing issues: setup and hold times • Finite State Machines (FSM) • With just a register and some logic, we can implement a state machine