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This project explores the scheduling challenges in multi-core systems, emphasizing the need for a more realistic model that treats a chip multi-processor (CMP) as a collection of heterogeneous cores operating at different frequencies and power profiles. Key milestones include the creation of a variability map, static profiling of applications, and the implementation of a novel scheduling algorithm within the CMP simulator. By analyzing performance variations, we aim to improve power efficiency and enhance system throughput in real-world applications.
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Variation Aware Application Scheduling in Multi-core Systems Lavanya Subramanian, Aman Kumar Carnegie Mellon University {lsubrama, amank}@andrew.cmu.edu Website: http://www.cs.cmu.edu/~amank/
Document Map • Problem Statement • Milestones • Overview of Project • Static Profiling • Variation Map Construction • Variability incorporation in BLESS • Results
Problem Statement (Aide-mémoire) • The perspective of a chip multi processor being a homogenous set of cores is not a practical one. • A CMP has to be relooked as: • a collection of heterogeneous cores • each core operating at different frequency • each core with a different power profile
Milestones • Milestone 1.1: • Building variability information into the CMP simulator. • Static profiling of applications. • Milestone 2: • Building a scheduler into the CMP simulator. • Milestone 3: • Implementing and analyzing the proposed scheme against the baseline algorithms.
Static Profiling • Simulate SPEC 2000 benchmarks on Wattch/Sim-GALS • Extract • Memory instruction dynamic power per instruction • Non-memory instruction dynamic power per instruction • Core average leakage power per cycle Power Model
Static profiling (Results) Tech: 45 nm Sim GALS
Variation Map Construction • Generate Leff variation map from Varimap tool • Calculate Leakage Variation • Based on Leff variation using SPICE and MATLAB • Calculate Frequency Variation (Base : 3GHz) • Based on Leff variation using MATLAB Tech: 45 nm Frequency Model (Built-in Variations) Power Model (Built-in Variations)
Variability per CORE • Read the Frequency/Leakage maps in BLESS • Compute Power/Performance based on Variability information Frequency Model (Built-in Variations) C1 C2 C3 C4 C1 C2 C3 C4 C5 C6 C7 C8 C5 C6 C7 C8 Power Model (Built-in Variations) C9 C10 C11 C12 C9 C10 C11 C12 C13 C14 C15 C16 C13 C14 C15 C16
Variability per CORE (Results) • Same Application on 16 Processors • 4 Applications on 16 Processors