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Trends in CMOS Image Sensor Technology and Design

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  1. Trends in CMOS Image SensorTechnology and Design Abbas El Gamal Department of Electrical Engineering Stanford University

  2. CCD Image Sensors • High QE and low dark current • Serial readout: • Slow readout • Complex clocking and supply requirements • High power consumption • Cannot integrate circuitry on chip

  3. CMOS Image Sensors • Memory-like readout: • Enables high speed operation • Low power consumption • Region of interest • Integration • Enable new applications: • Embedded imaging • High dynamic range • Biometrics • 3D imaging Reset Word Row Decoder Word Bit Pixel Bit Column Amplifiers / Caps Column ADC / Mux

  4. 200,000 180,000 CMOS 160,000 CCD 140,000 120,000 Thousands of Units 100,000 80,000 60,000 40,000 20,000 0 2001 2002 2003 2004 2005 2006 Year Image Sensor Market Source: In-Stat/MDR, 8/02

  5. CMOS Image Sensors Today • Most sensors: • application-specific (optical mouse) • low end (PC, toys) • Fabricated in old (0.6-0.35mm) processes • limited integration • Lower performance than CCDs: • Not used in digital cameras • Some exceptions (Canon D30/D60)


  6. Technology and Design Trends • Recent developments in: • Silicon processing • Color Filter Array and Microlens • Miniaturized packaging • Pixel design • Camera-on-chip • Promise to broaden CMOS image sensor applicability and enhance their performance

  7. This Talk • Silicon processing: • Sub-micron CMOS process modifications • Triple-well photodetector • Applications of modified processes: • Integrated color pixel • Multi-mega pixel sensors • Camera-on-chip integration • Pixel-level ADC – Digital Pixel Sensor • High Frame Rate Sensors and Applications • High dynamic range

  8. Scaling • CMOS image sensors have benefited from scaling: • smaller pixels • higher fill factor • greater pixel functionality (PPS  APS) • Need 0.18mm and below process for camera-on-chip integration

  9. Problems with standard CMOS • Low photoresponsivity -- shallow junctions, high doping • High junction leakage -- STI, salicide • High transistor leakage – off-current, thin gate oxide • Poor analog circuit performance Wong IEDM’96

  10. Microlens Overcoat Microlens Microlens Spacer Color Filter Color Filter Color Filter Color Filter Planarization Layer Improving Photoresponsivity • Deeper non-silicided lightly doped diode junctions (NW/PSUB, Ndiff/PSUB) • High transmittance SiON materials • Micro-lens and CFA integration SEM photograph of 3.3mm pixel Courtesy of TSMC

  11. QE of 0.18m CMOS Photodiode Quantum Efficiency Wavelength (nm) Courtesy of TSMC/Pixim

  12. Reducing Leakage • Junction leakage reduction: • Non-silicided double-diffused source/drain implants • Hydrogen annealing • Pinned-diode • Transistor leakage reduction: • Thick gate oxide transistors • Thresholds adjusted to increase voltage swing • Leakages of sub 1nA/cm2 achieved Wuu, IEDM, 2001

  13. Drawbacks of Color Filter Array • Loss of resolution • aliasing • Color cross-talk • Increase microlens to photodetector distance • Adds manufacturing steps and cost

  14. Column Out Green Column Out Blue Column Out Red Vn Vp Vn Reset Reset Vcc Vcc Vcc Row Select Row Select Row Select N Ldd P Well N Well P Substrate Triple-Well Photodetector (Foveon)

  15. Triple-well • Advantages: • No loss of resolution • Elimination of photon loss due to CFA • Elimination of color cross-talk • Challenges: • Larger pixel size – less pixels than standard sensors for same area • High spectral overlap between three color channels • Fabrication and circuit operation ?

  16. Green Blue Red 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 450 500 550 600 650 700 Spectral Response 1 Courtesy Foveon, Dick Lyon 0.9 0.8 Triple-Well 0.7 0.6 Relative Response 0.5 0.4 0.3 0.2 0.1 0 400 450 500 550 600 650 700 Courtesy TSMC CFA Relative Response Wavelength (nm)

  17. Integrated Color Pixel Light filters using patterned metal layers Catrysse, IEDM, 2001

  18. Enabling CMOS Technology Smallest Period in CMOS Technology 0.13 um 0.18 um 0.25 um 400 500 600 700 800 900 1000 Wavelength (nm)

  19. Integrated Color Pixel • Using metal patterns above each photodetector, wavelength selectivity can be controlled • Needs 0.13um process or multiple layers in 0.18 for good selectivity in the visible range

  20. 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 Pixels with increasing gap width 400 500 600 700 800 900 Wavelength (nm) 1D ICPs under imaging conditions Transmittance

  21. 0.6 0.5 0.4 0.3 0.2 0.1 0 One layer Two layers Transmittance 400 500 600 700 800 Wavelength (nm) Multiple Layers in 0.18mm CMOS

  22. 0.6 0.5 0.4 0.3 0.2 0.1 0 Two layers (Aligned) Two layers (Offset) Transmittance 400 500 600 700 800 Wavelength (nm) Layer Alignment in 0.18mm CMOS

  23. 0.6 0.5 0.4 0.3 0.2 0.1 0 0.18 mm 0.15 mm 0.13 mm 400 500 600 700 800 Wavelength (nm) Scaling to 0.13mm CMOS 0.18 mm Transmittance 0.13 mm

  24. Multi-Mega Pixel Sensors • Memory-like readout of CMOS image sensors an advantage over CCDs (Kozlowski, et al, IEDM, 1999) • Recent examples: • Kodak DCS Pro 14n (13.7 Megapixels) • Canon 1Ds (11 Megapixels) • Foveon 10X (10 Megapixel Triple-Well)

  25. Camera-on-Chip Integration Analog Proc & ADC Image Sensor ImageSensor & ADC ASIC Camera-on-chip Memory Memory ASIC PC-Board PC-Board Today Future

  26. Camera-on-chip Applications

  27. Memory ADC Digital Pixel Sensor (DPS) • Developed at Stanford (under PDC program) • ADC per pixel and all ADCs operate in parallel • Advantages: • Better technology scaling (integration) than APS • Very high speed digital readout • No column read noise or Fixed Pattern Noise

  28. Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Pixel Block Row Address Decoder Sense Amplifiers and Latches DPS Block Diagram

  29. High Speed DPS Chip • 0.18m CMOS • 352 x 288 pixels (CIF) • 9.4m x 9.4m pixels • 37 transistors/pixel • 3.8 million transistors • 8 bit single slope ADC and memory / pixel • 64 wide digital output bus at 167 MHz Kleinfelder, ISSCC, 2001

  30. Pixel Schematic Data I/O Reset V Reset PG Tx RAMP Read Thick-oxide Sensor Comparator 8-bit Memory

  31. Gray Code Counter 8 RAMP + Memory _ Input 8 Comp Out Digital Out ADC Operation Counter (Gray Code) Latched Value RAMP Input Comp Out 1 0 0 Memory Loading Memory Latched

  32. Video Sequence at 10,000 FPS

  33. Video Sequence at 700 FPS

  34. High Frame Rate Applications • High frame rate enables new still and video imaging applications: • Dynamic range extension • Motion blur prevention • Optical flow estimation • Motion estimation • Tracking • Super-resolution

  35. DSP Multiple-Capture Single-Image • Operate sensor at high frame rate • Process high frame rate data on-chip • Output data at standard rates • Integration of sensor with embedded DRAM and DSPs enables low cost implementation (Lim‘01)

  36. HDR via Multiple Capture T 2T 4T 8T 16T 32T

  37. HDR Image • Use Last-Sample-Before-Saturation Algorithm

  38. HDR Example Two captures of same high dynamic range scene Courtesy of Pixim

  39. CCD2 DPS HDR Comparison CCD1 DPS Courtesy of Pixim

  40. HDR Image via Multiple Capture

  41. Long exposure Short exposure Input Extending DR at Low Illumination • For given exposure time, LSBS only extends DR at high illumination -- Read noise is not reduced • Increasing exposure time limited by motion blur • Liu, ICASSP, 2001 describe an algorithm for extending DR at low illumination and preventing motion blur

  42. 60 50 40 30 20 10 0 Weighted Averaging Last Sample Before Saturation Single Capture DR=47dB SNR (dB) DR=85dB DR=77dB iph(fA) SNR and DR Enhancement 10-1 100 101 102 103

  43. 10 ms 0 ms 20 ms 40 ms 50 ms 30 ms 65 Image Capture Example

  44. High Dynamic Range Image Estimation / Motion Prevention LSBS

  45. DPS Imaging Array Frame Memory SIMD Processor Integration Beyond Camera-on-chip Lim, SPIE, 2001

  46. Summary

  47. Transistors Per Pixel 5mm pixel with 30% fill factor 512 256 128 64 32 16 8 4 2 1 # Transistors 0.35 0.25 0.18 0.15 0.13 0.10 0.07 0.05 Technology (m) ITRS Roadmap

  48. Motivation • PPS/APS do not scale well with technology: • Analog scaling problems • Sensitive to digital noise coupling • Modified 0.18mm CMOS enables camera-on-chip: • low cost and power consumption • Digital Pixel Sensor: • Scales well and less sensitive to digital noise • Can operate at high frame rate • Integration + high frame rate can be used to enhance sensor performance beyond CCDs

  49. Current Pixel Architectures • Passive Pixel (PPS): • Small pixel, large fill factor • Slow readout, low SNR • Reading is destructive • Active Pixel (APS): • Larger pixel, lower fill factor • Faster readout, higher SNR • Most popular architecture

  50. Microlens Overcoat Microlens Microlens Spacer Color Filter Color Filter Color Filter Color Filter Planarization Layer Micro-lens and CFA Integration SEM photograph of 3.3mm pixel Courtesy of TSMC