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Lecture 21: Voltage/Current Buffer Freq Response. Prof. Niknejad. Lecture Outline. Last Time: Frequency Response of Voltage Buffer Frequency Response of Current Buffer Current Mirrors Biasing Schemes Detailed Example. Common-Collector Amplifier. Procedure: Small-signal two- port model

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## Lecture 21: Voltage/Current Buffer Freq Response

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**Lecture 21:Voltage/Current Buffer Freq Response**Prof. Niknejad**Lecture Outline**• Last Time: Frequency Response of Voltage Buffer • Frequency Response of Current Buffer • Current Mirrors • Biasing Schemes • Detailed Example University of California, Berkeley**Common-Collector Amplifier**• Procedure: • Small-signal two-port model • Add device (andother) capacitors University of California, Berkeley**Two-Port CC Model with Capacitors**Gain ~ 1 Find Miller capacitor for C -- note that the base-emitter capacitor is between the input and output University of California, Berkeley**Voltage Gain AvC Across C**Note: this voltage gain is neither the two-port gain nor the “loaded” voltage gain University of California, Berkeley**Bandwidth of CC Amplifier**Input low-pass filter’s –3 dB frequency: Substitute favorable values of RS, RL: Model not valid at these high frequencies University of California, Berkeley**CB Current Buffer Bandwidth**Same procedure: startwith two-port model and capacitors University of California, Berkeley**Two-Port CB Model with Capacitors**No Miller-transformed capacitor! Unity-gain frequency is on the order of T for small RL University of California, Berkeley**Summ of Single-Stage Amp Freq Resp**• CE, CS: suffer from Miller-magnified capacitor for high-gain case • CC, CD: Miller transformation nulled capacitor “wideband stage” • CB, CG: no Millerized capacitor wideband stage (for low load resistance) University of California, Berkeley**CMOS Diode Connected Transistor**• Short gate/drain of a transistor and pass current through it • Since VGS = VDS, the device is in saturation since VDS > VGS-VT • Since FET is a square-law (or weaker) device, the I-V curve is very soft compared to PN junction diode • What’s the input impedance of circuit? University of California, Berkeley**Diode Equivalent Circuit**Equivalent Circuit: University of California, Berkeley**The Integrated “Current Mirror”**• M1 and M2 have the same VGS • If we neglect CLM (λ=0), then the drain currents are equal • Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS1 • We say that the current IREF is mirrored into iOUT • Notice that the mirror works for small and large signals! High Res Low Resis University of California, Berkeley**Current Mirror as Current Source**• The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET • M2 acts like a current source to the rest of the circuit University of California, Berkeley**Small-Signal Resistance of I-Source**University of California, Berkeley**Improved Current Sources**Goal: increase roc Approach: look at amplifier output resistance results … to see topologies that boost resistance Looks like the output impedance of a common-source amplifier with source degeneration University of California, Berkeley**Effect of Source Degeneration**• Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance • Output impedance is boosted by factor University of California, Berkeley**Cascode (or Stacked) Current Source**Insight: VGS2 = constant AND VDS2 = constant Small-Signal Resistance roc: University of California, Berkeley**Drawback of Cascode I-Source**Minimum output voltage to keep both transistors in saturation: University of California, Berkeley**Current Sinks and Sources**Sink: output current goes to ground Source: output current comes from voltage supply University of California, Berkeley**Current Mirrors**Idea: we only need one reference current to set up all the current sources and sinks needed for a multistage amplifier. University of California, Berkeley

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