Prototype System Block Diagram Upgrade Review

1. Design ReviewSR BPM Upgrade Tony Pietryla December 2, 2005

2. Prototype System Block Diagram • Receiver Interface • Buffer Position and Intensity signals • Receive control signals for receiver • Two 14-bit ADCs • Stratix II FPGA

3. Prototype Data Acquisition Chassis Stratix II FPGA 2 Channel ADC Coldfire IOC

4. Prototype Receiver Interface Backplane Receiver Receiver Interface Receiver Housing/Heatsink

5. Lab Test Setup • Tests performed with: • CW signal from generator, Dx & Dy terminated on receiver, or • 100Hz tone applied to ADC inputs

6. Lab Measurement – Calibration Data Scope Measurement: 14.35mV Measured Output: 14.74mV Scope Measurement: 2.82mV Measured Output: 2.96mV SRS DS360 Function Generator 100Hz Input directly into the ADC

7. Lab Noise Measurement – RMS Motion 1Hz – 1kHz • CW input using filter comparator and WJ receiver • Both delta inputs on receiver were terminated • 60Hz signal approximately 85nm rms.

8. Lab Noise Measurement – RMS Motion 200kHz – 44MHz • CW input using filter comparator and WJ receiver • Both delta inputs on receiver were terminated

9. Lab Measurement – Long Term Drift • CW input using filter comparator and WJ receiver • Both delta inputs on receiver were terminated • Result: 0.91mm pk-pk per 0.2 °C 4.10 mm pk-pk 0.9 °C pk-pk

10. Sector 38 (A:P3) Test Setup • The four button signals are combined then split to eliminate beam motion prior to the filter comparator

11. Beam Based Calibration • All resolution numbers and graphs were converted to mm using a calculated value of 14.28 mm/mV • Experiments were performed to determine the calibration of the prototype unit by changing a corrector and measuring the response • Measured response of S35A:P3, S37A:P3 and prototype connected to S38A:P3 buttons • Took average of S35A:P3 and S37A:P3 responses and applied to S38A:P3 • 14-bit ADC resolution = 122.07mV/count • Result: • Horizontal = 15.3 mm/mV • Vertical = 17.5 mm/mV

12. Single Bunch Fill Pattern – 1Hz to 1kHz • 5mA stored beam • Back-to-back splitters • 5 samples per bunch

13. 24 Bunch Fill Pattern – 1Hz to 1kHz • 102mA stored beam • Back-to-back splitters • 4 samples per bunch

14. 324 Bunch Fill Pattern – 1Hz to 1kHz • 102mA stored beam • Back-to-back splitters • All samples used

15. Long Term Drift – 24 Bunch Fill Pattern • Back-to-back splitters • 4 samples per bunch • Result: 0.93mm pk-pk per 0.2 °C 4.65mm pk-pk 1 °C pk-pk

16. Tcl/Tk Application for Manipulating Control Bits 4 samples Data portion of waveform Data portion of waveform

17. Original BPM Specification 1 24 Bunch or greater 2 Stored Beam, Single or Multiple Bunches 3 24 hours, ± 0.2 Celsius

18. BPM Upgrade Specification and Compliance Table 1 24 Bunch or greater 2 Stored Beam, Single or Multiple Bunches 3 24 hours, ± 0.2 Celsius