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ARM7TDMI-S CPU

ARM7TDMI-S CPU. MultiMarket Semiconductors BL Standard ICs - Microcontrollers February 2004. ARM Architecture. Thumb state Instruction set Processor Modes Register usage Interrupt Handling 3-stage Pipeline. ARM7TDMI-S. The ARM7TDMI-S is based on ARM7 core 3 stage pipeline

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ARM7TDMI-S CPU

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  1. ARM7TDMI-S CPU MultiMarket Semiconductors BL Standard ICs - Microcontrollers February 2004

  2. ARM Architecture • Thumb state • Instruction set • Processor Modes • Register usage • Interrupt Handling • 3-stage Pipeline

  3. ARM7TDMI-S The ARM7TDMI-S is based on ARM7 core • 3 stage pipeline • Von Neumann architecture • CPI ~1.9 • T: Thumb instruction set • D: includes debug extensions • M: enhanced multiplier (32x8) with instructions for 64-bit results • I: core has EmbeddedICE logic extensions • S: fully synthesisable (soft IP)

  4. Thumb State

  5. Thumb state • ARM uses a 32-bit architecture with a subset of 16-bit instructions, still using 32-bit data and registers. • Set of instructions re-coded into 16 bits • Improved code density by ~ 30% • saving program memory space • In Thumb state only the program code is 16-bit wide • after fetching the 16-bit instructions from memory, they are de-compressed to 32 bit instructions before they are decoded and executed • all operations are still 32-bit operations

  6. 31 1 0 BX 31 1 0 0 ARM and Thumb Interworking • Switch between ARM state and Thumb state using BX instruction • In ARM state: BX<condition> Rn • In Thumb state: BX Rn Rn n: 0-15 ARM / Thumb selection 0: ARM state 1: Thumb state Destination address

  7. Instruction Set

  8. ARM Instruction Set • All instructions are 32-bits long • Many instructions execute in a single cycle • Most of the ARM Instructions can be conditionally executed • Could be divided into six broad classes of instruction • Branch instructions • Data Processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions

  9. Thumb Instruction Set • All instructions are 16-bits long • Most of the Thumb Instructions cannot be conditionally executed • Thumb instruction set is subset of ARM instruction set • It takes more instructions in Thumb to do the same job in ARM resulting in a performance penalty

  10. Processor Modes

  11. Processor Modes(1) ARM has seven operating modes • User unprivileged mode under which most applications run • FIQ entered, when a high priority (fast) interrupt is raised • IRQ general purpose interrupt handling • Supervisor protected mode for the operating system entered on reset or software interrupt instruction • System privileged mode using same registers as user mode • Abort used to handle memory access violations • Undefined used to handle undefined instructions

  12. Processor Modes(2) Privileged Modes Exception Modes

  13. Privileged and Exception Modes • Entered when a specific exception occurs • Each mode has additional registers to prevent corruption • On Reset ARM core is in Supervisor mode • Have access to system resources • Can change modes freely using ARM instructions

  14. User Mode & System Mode • User Mode: • User mode has access to limited system resources • Cannot change modes freely within User mode • User program can make a supervisor call using the SWI instruction(SWI- Software Interrupt but is usually called Supervisor call) • System Mode: • System mode is similar to User mode but used by OS which needs access to system resources (Privileged) • System mode also used during nested interrupt handling

  15. ARM Registers

  16. Registers (1) An ARM core has 37 registers (32-bits wide) • General purpose registers • 1 program counter • 30 general purpose registers • Status registers • 1 current program status register(CPSR) • 5 saved program status registers(SPSR) These registers are not all accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

  17. Registers (II) • Depending on processor mode one of several banks is accessible. Each mode can access • the program counter r15 (PC) • a particular r13 (stack pointer SP) and r14 (subroutine link register, LR) • a particular set of r0-r12 registers • the current program status register (CPSR) • Privileged modes (except System mode) can also access • a particular SPSR (saved program status register)

  18. Register Banking User and System r0 r1 r2 r3 r4 Banked registers r5 r6 FIQ IRQ Supervisor Abort Undefined r7 r8_fiq r8 r9_fiq r9 r10_fiq r10 r11_fiq r11 r12_fiq r12 r13_fiq (SP) r13_irq (SP) r13_svc (SP) r13_abt (SP) r13_und (SP) r13 (SP) r14_fiq (LR) r14_irq (LR) r14_svc (LR) r14_abt (LR) r14_und (LR) r14 (LR) r15 (PC) SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und CPSR

  19. Registers in Thumb State • The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • eight general registers r0 - r7 • the program counter PC • a Stack pointer SP • a Link register LR • the current program status register CPSR • In Thumb state, the high registers (r8 - r12) are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage

  20. r0 r0 r1 r1 r2 r2 Thumb state Low registers r3 r3 r4 r4 r5 r5 r6 r6 r7 r7 r8 r9 r10 Thumb state High registers r11 r12 r13 (SP) r13 (SP) r14 (LR) r14 (LR) r15 (PC) r15 (PC) CPSR CPSR SPSR SPSR Thumb vs. ARM Thumb State ARM State

  21. Register Overview User and System FIQ IRQ Supervisor Abort Undefined r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 Thumb state Low registers r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8_fiq r8 r8 r8 r9_fiq r9 r9 r9 r9 r9 r10_fiq r10 r10 r10 r10 r10 r11_fiq r11 r11 r11 r11 r11 Thumb state High registers r12_fiq r12 r12 r12 r12 r12 r13_fiq (SP) r13_irq (SP) r13_svc (SP) r13_abt (SP) r13_und (SP) r13 (SP) r14_fiq (LR) r14_irq (LR) r14_svc (LR) r14_abt (LR) r14_und (LR) r14 (LR) r15 (PC) r15 (PC) r15 (PC) r15 (PC) r15 (PC) r15 (PC) CPSR CPSR CPSR CPSR CPSR CPSR SPSR_svc SPSR_fiq SPSR_irq SPSR_abt SPSR_und

  22. 31 30 29 28 24 23 16 15 8 7 6 5 4 0 27 N Z C V Q J I F T mode Control bits Condition code flags Reserved Program Status Register (1) • Condition Code Flags • N: Negative or less than • Z: Zero • C: Carry or borrow or extend • V: Overflow To not corrupt reserved bits, a read-modify-write strategy should be applied to change PSR bits.

  23. 31 30 29 28 24 23 16 15 8 7 6 5 4 0 27 N Z C V Q J I F T mode Control bits Condition code flags Reserved Program Status Register (2) • Mode Bits • Interrupt Disable Bits • I: IRQ interrupts disable • F: FIQ interrupts disable • T Bit • Thumb mode (when set) • ARM mode (when cleared)

  24. Program Counter (r15) • When the processor is executing in ARM state • all instructions are 32 bits wide • all instructions must be word aligned • bits [31:2] contain the PC, bits [1:0] are zero (instructions cannot be halfword or byte aligned) • When the processor is executing in Thumb state • all instructions are 16 bits wide • all instructions must be halfword aligned • bits [31:1] contain the PC, bit [0] is zero (instructions cannot be byte aligned)

  25. Interrupt Handling

  26. ARM Exception Vectors and processor mode

  27. . . . FIQ 0x1C IRQ 0x18 (Reserved) 0x14 Data Abort 0x10 Prefetch Abort 0x0C Software Interrupt 0x08 Undefined Instruction 0x04 Reset 0x00 Exception Vectors table

  28. SPSR_<mode> CPSR 8 7 6 5 4 0 CPSR: I F T mode Control bits Exception Handling • Entering an exception the ARM core • saves the address of the next instruction in the appropriate LR • copies the CPSR into the appropriate SPSR • sets appropriate CPSR bits • interrupt disable bits • mode field bits • if running in Thumb state, enter ARM state* • forces PC to fetch next instruction from relevant exception vector *: all exceptions switch to ARM state! r14_<mode> (LR) r15 (PC)

  29. PC - offset r14_<mode> (LR) r15 (PC) SPSR_<mode> CPSR 8 7 6 5 4 0 CPSR: I F T mode Control bits Leaving Exception(1) • To leave an exception, the exception handler must • copy SPSR back into CPSR (automatically restoring also I, F and T) • move contents of current LR minus offset* to PC *: varies according to type of exception: 2, 4

  30. PC - offset Leaving Exception-Example(2) • After servicing IRQ execute the following instruction SUBS PC,R14_irq,#4 • This restores both PC and CPSR SPSR_irq> CPSR r14_<irq> (LR) r15 (PC)

  31. Multiple Exceptions • Exception priorities • When multiple exceptions arise at the same time, a fixed priority sytem determines the order in which they are handled

  32. FIQ-Why is it called so ? • This mode has its own set of banked registers from R8-R12. Hence no or minimal stack operations are required • FIQ is the last interrupt vector in the vector table. Hence jump is not needed to reach ISR • ARM recommends only one interrupt source to be classified as FIQ

  33. Interrupt Latency • Latency could be between 5 to 27 processor clocks • Ask customers to refer to ARM7TDMI-S Technical Reference Manual for details

  34. Instruction Pipeline

  35. Instruction Pipeline • The ARM7TDMI-S core uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously • The Program Counter (PC) points to the instruction being fetched rather than to the instruction being executed • During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory

  36. 3-Stage Instruction Pipeline ARM PC PC - 4 PC - 8 Thumb PC PC - 2 PC - 4 Fetch Instruction Fetched from Memory Thumb only: Thumb instruction decompressed to ARM instruction Instruction decoded Registers read from Register Bank, Shift and ALU operations performed, Registers written back to Register Bank Decode Execute

  37. 6 8 1 2 3 4 5 7 Cycle ADD Fetch Decode Execute SUB Fetch Decode Execute MOV Fetch Decode Execute AND Fetch Decode Execute ORR Fetch Decode Execute EOR Fetch Decode Execute CMP Fetch Decode RSB Fetch Optimal Pipelining • In this example it takes 6 clock cycles to execute 6 instructions • All operations are on registers (single cycle instructions) • Clock cycles per instruction (CPI) = 1

  38. BL 0x8000 Fetch Decode Execute Linkret Adjust X 0x8004 Fetch Decode X 0x8008 Fetch ADD 0x8FEC Fetch Decode Execute SUB 0x8FF0 Fetch Decode Execute MOV 0x8FF4 Fetch AND 0x8FF8 Fetch 5 7 1 2 3 4 6 Cycle Branch Pipeline Example • Branches break the pipeline • Example in ARM state Decode

  39. Reference • ARM Architecture Reference Manual • Available with ARM tools • Also available on PDF • ARM System-on-Chip Architecture • By Steve Furber

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