
Digital Systems Design 2. VHDL: Modeling Behaviour Ref. “VHDL Starter’s Guide”, Sudhakar Yalamanchili, Prentice Hall, 1998. Modeling Behavior with VHDL.
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VHDL: Modeling Behaviour
Ref. “VHDL Starter’s Guide”, Sudhakar Yalamanchili, Prentice Hall, 1998
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R
W
DO
DI
Memory
ADDR
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process_name: process (signal1, signal2, …, signalN)
-- declarative region
variable variable-names: variable-type;
type type-name is (value-list);
constant constant-name: type-name := value;
begin
-- process body region where conventional programming constructs can be used.
end process process_name;
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use IEEE.std_logic_1164.all;
use WORK.std_logic_arith.all;
entity memory is
port (address, write_data: in std_logic_vector(31 downto 0);
MemWrite, MemRead: in std_logic;
read_data: out std_logic_vector(31 downto 0)
end memory;
architecture memory_func of memory is
type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
begin -- for architecture
mem_process: process (address, write_data)
variable data_mem: mem_array := (
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”),
to_stdlogicvector(X”00000000”));
variable addr: integer;
begin -- for process
-- the following conversion function is in WORK.std_logic_arith package
addr := to_integer (address (2 downto 0));
if MemWrite = ‘1’ then
data_mem(addr) := write_data;
elsif MemRead = ‘1’ then
read_data <= data_mem(addr) after 10 ns;
end if;
end process mem_process;
end memory_func;
VHDL – Memory ExampleVeton Këpuska
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if boolean-expression then
sequential-statement
end if;
if boolean-expression then
sequential-statement
else
sequential-statement
end if;
if boolean-expression then
sequential-statement
elsif boolean-expression then
sequential-statement
…
elsif boolean-expression then
sequential-statement
else
sequential-statement
end if;
Programming ConstructsVeton Këpuska
case expression is
when choices => sequential-statement;
…
when choices => sequential-statement;
end case;
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library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port (a,b: in std_logic;
sum,carry: out std_logic
end half_adder;
architecture half_adder_func of half_adder is
begin
sum_process: process(a,b)
begin
if (a=b) then
sum <= ‘0’ after 5 ns;
else
sum <= (a or b) after 5 ns;
endif
end process sum_process;
carry_process: process(a,b)
begin
case a is
when ‘0’ =>
carry <= a after 5 ns;
when ‘1’ =>
carry <= b after 5 ns;
when others =>
carry <= ‘X’ after 5 ns;
end case;
end process;
end half_adder_func;
Programming ConstructsVeton Këpuska
while boolean-expression loop
sequential-statement;
…
sequential-statement;
end loop;
for boolean-expression in range loop
sequential-statement;
…
sequential-statement;
end loop;
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0110
X 0101
----------
0110
+ 0000
+ 0110
+0000
----------
0011110
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Multiplier
Multiplicand
MD
AC
MQ
0110
0000
|0101
+
0110
0110
|0101
ADD
0111
10|01
ADD
0011
0|010
SHIFT
0011
110|0
SHIFT
+
+
0000
0000
0011
0|010
ADD
0011
110|0
ADD
0001
10|01
SHIFT
0001
1110|
SHIFT
+
0110
Veton Këpuska
use IEEE.std_logic_1164.all;
use WORK.std_logic_arith.all;
entity mult32 is
port (multiplicant, multiplier: in std_logic_vector(31 downto 0);
product: out std_logic_vector(63 downto 0)
end mult32;
architecture mult32_func of mult32 is
constant module_delay: Time := 10 ns;
begin -- architecture
mult_process: process (multiplicand, multiplier)
variable product_register: std_logic_vector(63 downto 0) := x’0000000000000000’;
variable product_register: std_logic_vector(31 downto 0) := x’00000000’;
begin -- process
multiplicant_reregister := multiplicant;
product_register(63 downto 0) := x’00000000’& multiplier;
--
-- repeated shift-and-add loop
--
for index in 1 to 32 loop
if product_register(0) = ‘1’ then
product_register(63 downto 32) := product_register(63 downto 32)+multiplicant_register(31 downto 0);
end if;
--perform right shift with zero fill
product_register(63 downto 0) := ‘0’ & product_register (63 downto 1);
end loop;
-- write result to output port
product <= product_register after module_delay;
end process mult_process;
end mult32_func;
Example of the use of the loop constructsVeton Këpuska
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use IEEE.std_logic_1164.all;
entity full_adder is
port (in1,in2, c_in: in std_logic;
sum,c_out: out std_logic
end full_adder;
architecture full_adder_func of full_adder is
signal s1, s2, s3:std_logic;
constant delay : Time := 5 ns;
begin
HA1: process (in1, in2) -- process describing the first half adder
begin
s1 <= (in1 xor in2) after delay;
s2 <= (in1 and in2) after delay;
end process HA1;
HA2: process (s1, c_in) -- process describing the second half adder
begin
s1 <= (s1 xor c_in) after delay;
s2 <= (s1 and c_in) after delay;
end process HA2;
OR1: process (s2, s3) -- process describing two input-or gate
begin
c_out <= (s2 xor s3) after delay;
end process OR1;
endfull_adder_func;
Example of communicating process model of a full adderVeton Këpuska
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use IEEE.std_logic_1164.all;
entity asynch_dff is
port (R,S,D,Clk: in std_logic;
Q,Qbar: out std_logic
end asynch_dff;
architecture asynch_dff_func of asynch_dff is
begin
Dff_process: process (R,S,Clk)
begin
if (R = ‘1’) then
Q <= ‘0’ after 5 ns;
Qbar <= ‘1’ after 5 ns;
elsif (S = ‘1’) then
Q <= ‘1’ after 5 ns;
Qbar <= ‘0’ after 5 ns;
elsif (Clk’eventand Clk=‘1’) then
Q <= D after 5 ns;
Qbar <= (not D) after 5 ns;
endif;
end process Dff_process;
end asynch_dff_func;
D Flip-Flop with Asynchronous Set and Reset inputsVeton Këpuska
ACK – acknowledgment
transmit_data - Transmit data signal
Following example illustrates
The use of wait statement to control asynchronous communication between processes.
The ability to suspend the execution of a process at multiple points within the VHDL code.
4-phase handshake
Example of Asynchronous CommunicationVeton Këpuska
use IEEE.std_logic_1164.all;
entity handshake is
port (input_data: in std_logic_vector(31 downto 0);
end handshake;
architecture handshake_func of handshake is
signal transmit_data: std_logic_vector(31 downto 0);
signal RQ,ACK: std_logic;
begin
producer: process
begin
-- wait until input data becomes available
wait until input_data’event;
-- provide data as producer
transmit_data <= input_data;
RQ <= ‘1’;
wait until ACK = ‘1’;
RQ <= ‘0’;
wait until ACK = ‘0’;
end process producer;
consumer: process
variable receive_data: std_logic_vector(31 downto 0);
begin
-- wait until producer makes the data available
wait until RQ = ‘1’;
receive_data := transmit_data; -- read the data
transmit_data <= input_data;
ACK <= ‘1’;
wait until RQ = ‘0’;
ACK <= ‘0’;
end process consumer;
end handshake_func;
Example of Asynchronous CommunicationVeton Këpuska
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type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
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type state_type is (state0,state1,state2,state3);
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foriinvalue_array’range loop
…
my_var := value_array(i);
…
end loop;
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signal <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;
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library IEEE;
use IEEE.std_logic_1164.all;
entity periodic is
port (Z: out std_logic);
end periodic;
architecture periodic_func of periodic is
begin
process
begin
Z <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;
wait for 50 ns;
end process;
end periodic_func;
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use IEEE.std_logic_1164.all;
entity two_phase is
port (phi1,phi2,reset: out std_logic);
end two_phase;
architecture two_phase_func of two_phase is
begin
reset_process: reset <= ‘1’, ‘0’ after 10 ns;
clock_process: process
begin
phi1 <= ‘1’, ‘0’ after 10 ns;
phi2 <= ‘0’, ‘1’ after 12 ns, ‘0’ after 18 ns;
wait for 20 ns;
end process clock_process;
end two_phase_func;
Two phase non-overlapping clocks
Generating Clocks and Periodic WaveformsVeton Këpuska
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use IEEE.std_logic_1164.all;
entity state_machine is
port (reset,clk,x: in std_logic;
z: out std_logic;
end state_machine;
architecture state_machine_func of state_machine is
type state_type is (state0, state1);
signal state,next_state: state_type := state0;
begin
comb_process: process (state, x)
begin
case state is
when state0 =>
if x = ‘0’ then
next_state <= state1;
z <= ‘1’;
else
next_state <= state0;
z <= ‘0’;
endif
when state1 =>
if x = ‘1’ then
next_state <= state0;
z <= ‘0’;
else
next_state <= state1;
z <= ‘1’;
endif
end case;
end process comb_process;
Example of Finite State MachineSynchronous ImplementationVeton Këpuska
clk_process: process
begin
-- wait until raising edge
wait until (clk’event and clk = ‘1’);
-- check for reset
if reset = ‘1’ then
state <= state_type’left;
else
state <= next_state;
end if;
end process clk_process;
end state_machine_func;
Veton Këpuska
use IEEE.std_logic_1164.all;
entity state_machine is
port (reset,clk,x: in std_logic;
z: out std_logic;
end state_machine;
architecture state_machine_func of state_machine is
type state_type is (state0, state1);
signal state,next_state: state_type := state0;
begin
output_process: process (state, x)
begin
case state is
when state0 =>
if x = ‘1’ then
z <= ‘0’;
else
z <= ‘1’;
endif
when state1 =>
if x = ‘1’ then
z <= ‘0’;
else
z <= ‘1’;
endif
end case;
end process output_process;
Example of Finite State MachineAsynchronous ImplementationVeton Këpuska
begin
-- set next_state depending upon
-- the current state and input signal
case state is
when state0 =>
if x = ‘1’ then
next_state <= state0;
else
next_state <= state1;
endif
when state1 =>
if x = ‘1’ then
next_state <= state0;
else
next_state <= state1;
endif
end case;
end process next_state_process;
clk_process: process
begin
-- wait until raising edge
wait until (clk’evnet and clk = ‘1’);
-- check for reset
if reset = ‘1’ then
state <= state_type’left;
else
state <= next_state;
end if;
end process clk_process;
end state_machine_func;
Example of Finite State Machine (cont.)Veton Këpuska
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