Digital Systems Design 1

1. Digital Systems Design 1 Design Conventions Veton Këpuska

2. Design Conventions • Need for Automation from the Design Process to Computer Hardware Fabrication => Computer Hardware Description Languages • Basic Conventions of AHPL (A Hardware Programming Language) will be presented. • More sophisticated notations and conventions will be introduced step-by-step through examples. • Any hardware description language including AHPL is based on the fact that most digital systems can be partitioned into a control section and section containing data registers and logic. Veton Këpuska

3. Data/Control Partitions • Any hardware description language including AHPL is based on the fact that most digital systems can be partitioned into a control section and section containing data registers and logic. DATA REGISTERS AND LOGIC Data Input Data Output Control Signals Branching Information CONTROL SEQUENTIAL CIRCUIT Control Inputs Control Outputs Veton Këpuska

4. Register Transfers • Much of activity of a Digital System consists of transferring of information from one register to another. • Example – a Boolean operation performed on the data contained in a register. • Digital Computer can thus be viewed as a collection of digital registers among which data may be transferred, with logical and arithmetic operations taking place during the transfers. • Major portion of the digital system design process deals with the process of establishing a schedule that defines each transfer and specifies the ordering and timing in which these transfers will take place. Veton Këpuska

5. Relationship of Actual Hardware and Hardware Design Language • Hardware mechanisms through which a register transfer can be accomplished will be described. • Corresponding Notation for expressing the simplest of these transfers as design language steps will also be presented. • Conventions: • Registers will be noted by strings of boldface italic capital letters: MA, PC, and AC. • Transfers of the contents of one register into another is indicated by an arrow “←“, e.g., AC ← MD • Note: Content of MD is transferred to AC. Veton Këpuska

6. Register Transfers (2) • Content of Source Register is not affected by the transfer from it. Previous Contend of Destination register is overwritten with new information. • In the following examples it is assumed that AC register is 4-bits long: AC ← 0, 0, 0, 0 # Clears AC register. AC ← 1, 1, 1, 1 # Sets AC register. Veton Këpuska

7. Synchronization • Large majority, if not all, of register transfers in digital systems are synchronized by a systems master clock. • Flip-flops are thus necessary to be equipped with master set and master clear inputs. • In RIC control section as well as data section is synchronized by the master clock. • All logic level changes on output lines from control unit will take place at the time of the trailing edge of a clock pulse. • The system will be referred as trailing-edge-triggered system. Veton Këpuska

8. Control Levels and Control Pulses • CSL – control signal • CSP – synchronized control pulse Control Sequential Circuit Clock CSL CSP CLOCK CSL Veton Këpuska

9. Example of Clocked Register TransferImplementation • BR ← AR Veton Këpuska

10. Timing of Data Transfers of Previous Example Veton Këpuska

11. Conditional Transfer Veton Këpuska

12. Transfer with Set and Clear • Example: Consider a logic circuit design problem where a 4-bit register of D flip-flops AR is to be set to: • AR = 1 if CSL1 = 1, • AR = 0 if CSL2 = 1, • AR←DR if CSL3 = 1. Veton Këpuska

13. Transfer with Set and Clear (2) • Solution: It is assumed that one and only one control signal can be 1 at any time instance. csl1, csl2 csl3 CSL1 BR[i]·CSL3 Veton Këpuska

14. Transfer with Set and Clear (3) • DAR[i]= CSL1 + (BR[i]·CLS3) Veton Këpuska

15. AHDL Constructs • AHPL allows specification of individual flip-flops during transfer. In addition it allows catenation of individual flip-flops and registers to form long vectors. For example: DR[2], DR[3], CR[0]← AR[3], AR[4], AR[5] • In addition, AHPL, supports specification of a continuous segment of a register (vector). For instance AR[2], AR[3] and AR[4] can be expressed as AR[2:4]. Example: DR[2:3], CR[0]← AR[3:5] Veton Këpuska

16. AHDL Logical Computations Constructs • Examples: AR← BR’ # Negation; each bit of register B is inverted CR← AR∨ BR# OR CR← AR∧ BR # AND Circuit realization of the latter expression is given in following diagram. Veton Këpuska

17. Logical Operation and Transfer Veton Këpuska

18. Busing • Until know we have only considered transfers between a single pair of registers. • An ability to gate the content from any register to any register is needed. • However, extension of direct method as presented in previous diagrams is not feasible: • Number of Logic Gates increases non-linearly (exponentially with second order) with the increase of the number of registers that need to be interconnected. • Number of inputs to each gate (fan-in) increases proportionally to number of registers. • Use of the Buses provides solution to this problem. The notation for a bus in AHPL is the same as for register except that it ends in the word “BUS”. Veton Këpuska

19. Direct Transfer Among a Group of Registers Veton Këpuska

20. Bus Connection of Registers Veton Këpuska

21. Bus Connection of Registers (2) • In the prior example the bus was referred to as IBUS. This similarity of notation to a register is made by choice to reflect the fact that a bus exhibits many characteristics of a register. • The transfer of data through a bus is a two-step process. Both steps can be accomplished in one clock period. The first step uses the control to route the data to the output of the bus. This operation differs from a register transfer in that data is not stored by a bus. A data vector will remain in the output of a bus only as long as the control level remains active (e.g., 1). • The symbol “=“ will be used to denote the routing of a data vector to the output of a bus. In previous example two choices are possible that are reflected in the connection statement bellow. IBUS = AR and IBUS = BR Veton Këpuska

22. Bus Connection of Registers (3) • Second step of triggering the bus output into the destination register is usually accomplished by the same clock pulse that terminates the control level holding the data on the bus. This operation is not different from that of transferring the contents of a register into a destination register. • This step is designated in AHPL as follows. CR← IBUS andDR← IBUS • Thus, since the transfer can occur in one clock period, it can be expressed by a single step with a AHPL statement: 5IBUS ← AR; DR←IBUS. Timing of this operation is illustrated in the figure bellow. Veton Këpuska

23. Timing of a Bused Data Transfer Veton Këpuska

24. Bus Connection of Registers (4) • The actual physical realization of a bus is more complex than a simple set of gates as implied by the previous diagram. Exact form will depend on the exact: • type of the input and output gates, • number of registers connected, and • a number of various factors that are beyond the score of this discussion. • The result of gating of more than one register onto the bus at the same time will depend on the exact form of the bus. In some cases the result may be a logical OR-ing of the data, in others the result may be unpredictable. • RIC architecture assumes that only one register may be gated onto the bus at a time. • On the other hand it is permissible to transfer the data into more than one register at once. Veton Këpuska

25. Register Direct and Bus Transfers • Both methods of register interconnection: • Separate gating, and • Busing, are used. • To suggest the possible hardware saving achieved through the use of a bus, lets suppose that it is desired that a path be made available for the transfer of information from any one of N registers to any one of M destination registers. • For separate gating/direct interconnection of registers it is required: • N*M – banks of AND gates, • M – banks of OR gates each. Veton Këpuska

26. Register Direct and Bus Transfers • Lets assume that there are B bits in each register and a unit cost for each “AND” and “OR” gate. The cost of the data paths is given by: • Cost of Direct Interconnection: M*B(N+1) • For Interconnection via a Bus: • N banks of AND gates • 1 bank of OR gates is required • Cost of Bus Interconnection is: B(N+1) • Conclusion: • If there interconnection of more than 2 registers is required than the use of busing will result in savings in hardware. • Architectures that do not require all possible paths between registers require specific analysis in case by case basis because generalization is not possible. Nevertheless, in spite of slightly more complex procedure of complexity analysis, the basic process is similar to the one just presented. • Remark: Detailed diagram of interconnections is highly impractical for actual sizes of registers, and also not necessary. Two possible versions that are in use are presented in the next slide. Veton Këpuska

27. Simplified Bus Network Notation Veton Këpuska

28. Simplified Bus Network Notation (2) Veton Këpuska

29. Intersystem Busing • Communication Bus – a cable used for physically interconnecting separate Digital Systems. • Busing is require in order to minimize number of interconnecting wires. • Illustration of intersystem bus wiring of four digital systems A, B, C, and D: • Each system must have capability to connect to the input of a bus called IOBUS. • Each system must have also access to output of IOBUS. • For illustration purposes only 1-bit of the bust for each of the four systems along with corresponding individual wires will be presented. • The hardware solution presented previously will be used to satisfy design problem. Veton Këpuska

30. Intersystem Bus Wiring Veton Këpuska

31. Sequencing of Control • Up to this point we have carefully described wiring and timing of control signals associated with individual register data transfers and the routing of those data vectors through buses. • However, the mechanism by which a sequence of such transfers is made possible is not being discussed. • It is this capability/mechanism that makes possible execution of register transfers as a function of previous result of execution, and thus enables processing of algorithms via hardware. • Thus, there must exist a hardware mechanism to provide for sequencing as well as notation for representing both fixed and conditional branches in sequences in a hardware description language (e.g., AHPL). • This sequencing and its notation is the subject of this section. • Next section will treat realization of the control sequential circuit as depicted in general description of a Digital System of the slide/page 3. Veton Këpuska

32. Example of a Data Selector • System Diagram of Data Selector System A X System C System B INREG [12] Z OUTREG [12] A[4] Control Unit inready outready Veton Këpuska

33. Example of Sequencing of Control • The function of system B is to delete those vectors for which the following is true: X[0:3]∧ X[4:7]∧ X[8:11]= (0, 0, 0, 0) • Data flow is ASYNCHRONOUS: • System A places a new vector X after it receives a logical 1 for duration of one-clock-period on line inready. • System C will accept a data vector Z from the set of 12 lines immediately after observing logical 1 for duration of one-clock-period on line outready. • Control signals inready and outready appear well in advance of the need for new data on lines X and well before the data will be changed on lines Z. This consideration is required in order to account for processing delay of the system B. Veton Këpuska

34. Generation of a One-Period Output Veton Këpuska

35. AHPL Description of Sequencing of Control:Hardware Control Sequence – Example 1. Veton Këpuska

36. Conditional Branching in AHPL • Fixed/Unconditional and Conditional Branching • Fixed Transfer: → (D) # D is a statement number → (F) # F is a function its value to be determined by a logical or algebraic computation. • Conditional Branching: • (f1(x1, …, xk), f2(x1, …, xk), …, fn(x1, …, xk))/(D1, D2, …, Dn) • fi(x1, …, xk) ∧ fj(x1, …, xk) = 0 ∀ i and j, and i ≠ j. Veton Këpuska

37. AHPL Examples of Branching • Two function branch: • → (IR[0]’, IR[0])/(10, 18). • Since next step is 18 following statement is equivalent to the above: • → (IR[0]’)/(10). • Fixed Branch of step 7 can be expressed in AHPL as: → (1). • Conditional step 5 of previous example may be written as: 5 → (s, s’)/(6, 1). • Again, since the next step is 6 the following is equivalent: 5 → (s’)/(1). Veton Këpuska

38. AHPL Branching • Each AHPL statement will consist of atransfer part and a branch part. • Transfer part will consist of zero or more transfer statements, output statements, or bus routes. • Branch part will follow the format of expression:(f1(x1, …, xk), f2(x1, …, xk), …, fn(x1, …, xk))/(D1, D2, …, Dn) Veton Këpuska

39. AHPL Example 1 (Cont.) Veton Këpuska

40. Optimization of AHPL • Clock pulse that executes a transfer of a AHPL statement also effects the branch operation of the same step. • Eliminate control flip-flop s from the design of the example 1 and replacing steps 4 and 5 by: • Null; ((A[0]∨A[1]∨A[2]∨A[3]),(A[0]∨A[1]∨A[2]∨A[3])’)/(5,1). • Ultimately the goal is to be able to generate from an English-language description of a digital system of any complexity an AHPL control sequence or a hardware description program that completely and unambiguously describes that system. Veton Këpuska

41. Example 2 • The following AHPL sequence describes a simple system that receives a vector X and makes it available as an output after a delay, subject to the control of input signals a and b. • If (a = b = 0), the vector is not transferred. • If (a = 0 and b = 1), the vector is transferred without modification. • If (a = 1 and b = 0), the vector is rotated one place right. • If (a = 1 and b = 1), the vector is rotated two places right. Veton Këpuska

42. Example 2 (Cont.) Veton Këpuska

43. Useful Remark: • AHPL Control Sequence of example 2 is only a partial description of the system without certain information. • The input and output lines were identified only verbally. • The number of bits in Rwas also indicated only verbally. • AHPL description should provide a complete specification of a digital system. • This will be made possible through the use of declaration statements, which will among other functions, specify register length and identify input/output lines. This topic will be subject of the next chapter. Veton Këpuska

44. Electronic Realization of the Control Unit • Control Unit of a Digital System is a Synchronous Finite-State Machine. • Each step may be regarded as a state with the branch statement associated with the step specifying the next state as a function of the inputs. • The outputs are the control signals send to Data Unit. • There are many possible approaches to control unit realization requiring varying number of flip-flops and varying amounts of combinatorial logic. • Trade-off between memory elements and the amount of combinatorial logic. • At one extreme – classical, minimal state, sequential circuit realization, • On the other – microprogrammed control unit (topic of the study in the second part of this course). Veton Këpuska

45. Electronic realization of the Control Unit (2) • Approach taken here is one flip-flop to be used per control state model as a hardwired realization of a control unit - This is in complete opposite spectrum from microprogramming approach. • In this model, only one flip-flop corresponding to the current control step will be in the “ON” (1) state, while all others will be in the “OFF” (0) state. • It is not a minimalistic approach to design. • However, it implies simple combinatorial logic. • It affords direct interpretation of an AHPL control sequence. • Translation of an AHPL sequence to this type of control does not require knowledge of formal sequential circuit synthesis. • It has been found that it is hard to improve on the overall economy of this approach. • It is also compatible with the concept of multiple active control states, which will be discussed in proceeding course. Veton Këpuska

46. Control Unit realization of a single AHPL step • 9 B← A;(f1, f2, f3)/(10, 20, 30). Veton Këpuska

47. Example 2 (Cont. 2) Veton Këpuska

48. Realization of Example 2 Veton Këpuska

49. Function-Level Simulation • Digital System can be simulated at several distinct levels: • Transistor Models of the Digital Circuits (gate-delay-level simulation). • Most accurate simulation (e.g., SPICE). • Prohibitively expensive (CPU-time) • Gate-level simulation divides time into finite increments (10-100 increments per clock period) • 10-100 more economical than gate-delay-level simulation. • Still can be CPU-time expensive. • Simulation via hardware description language (e.g., AHPL, VHDL, or other register transfer language). • This approach is referred to as function-level simulation. • Registers are represented by single words in the host (memory efficiency), • Only statements in an active control step are executed each clock period (cpu – efficiency). • Because of the precise one-to-one correspondence between the AHPL description of a clock-mode network and the network itself, execution of the AHPL description can be expected to give the same results as simulation of the network. • Function-level simulators use thus significantly less computer time than clock-mode event-driven simulation of the network level. Veton Këpuska

50. The Conditional Transfer • Conditional branch offers transfers between two or more alternatives. • Example: A← B if a = 0; D← C if a = 1; AHPL: Veton Këpuska