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  1. Timing and Event SystemS. Allison, M. Browne, B. Dalesio, J. Dusatko, R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S. Norum, D. Rogind, H. Shoaee, M. Zelazny

  2. Outline • Overview – HW Block Diagram and Reqts • Progress since Oct, 2006 • Outstanding Issues • Task List • HW Status & Long-Haul Fiber Issues

  3. Timing Architecture Linac main drive line ~ FIDO 119 MHz 360 Hz SLC MPG E V G P N E T I O C SLC pattern Events & Data LCLS Digitizer LLRF BPMs Toroids Cameras GADCs E V R I O C Events & Data TTL P N E T S T B m P TTL-NIM convert. Old klystrons SLC Trigs

  4. Hardware Block Diagram 2007 Commissioning Modulator Triggers Existing Control System Beam Path Acq and Calibration Triggers PADs and PACs BPM FEE Acc and Standby Triggers Timing Crate E V G F A N 1 F A N 2 P N E T I O C EVR EVR 1 EVR 2 EVR 3 I O C I O C 360Hz Fiducial RF Timing BPM Crates LLRF Crate 119MHz Clock Future MPS Beam Rate, Beam Path Fiber Distribution: Timing Pattern, Timestamp, Event Codes Triggers Triggers TORO FEE Trigger EVR 1 C A M 1 C A M 2 I O C 1 … EVR 4 C A M 7 C A M 8 I O C 4 F A N 3 EVR 1 C A M 1 I O C 1 ... EVR 8 C A M 8 I O C 8 EVR F A N 4 I O C Profile Monitor Crate Laser Steering Crate Toro Farc Crate … …

  5. Event System Requirements • Event Generator IOC: • Send out proper event codes at 360Hz based on: • PNET pattern input (beam code and bits that define beam path and other conditions) • Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc. • Future – event codes also based on new MPS and user input • Send out system timestamp with encoded pulse ID from PNET • Send out PNET pattern to be used by SLC-aware IOCs • Manage user-defined beam-synchronous acquisition measurement definitions • Check for match between user meas definitions and input PNET pattern at 360Hz and tag matches in outgoing pattern • MPS Algorithm Processors and Master Pattern Generator (MPG): • Rate-liming logic including beam “burst” and “single-shot” modes • Send out PNET pattern to EVG and CAMAC controls (for modulator triggers)

  6. Event System Requirements, cont • Event Receiver IOC: • Receive event pattern 8.3 msec before corresponding pulse • Set trigger delays, pulse widths, and enable/disable via user requests (not yet done on a pulse-by-pulse basis) • Perform beam-synchronous acquisition based on tags set by EVG in the pattern • Perform beam-synchronous acquisition for the SLC-aware IOC based on the PNET part of the event pattern • Set event code per trigger (triggering done in HW when event code received) • Process pre-defined records when specific event codes are received (not yet available)

  7. EVG Event Time Line – 4 Fiducials 360Hz Fiducial F3 (n=3) F1 (n=1) F2 (n=2) F0 (n=0) 2.8 5.6 Time (msec) 0 9.3 8.3 1.0 R3 HW starts sending event codes, starting with fiducial event code R2 R1 R0 Receive Fn+3 PNET, determine Fn+3 LCLS pattern, and advance pipeline (n-2->n-1->n) P3 P0 P2 P1 L2 L3 L0 L1 Send LCLS pattern Set Event Codes in Alt RAM based on the last patterns for Fn+1 E3 E4 E1 E2 B-3 120Hz BEAM B0

  8. Trigger Event Time Line – 1 Beam Pulse (B0) Record processing (event, interrupt) Hardware Triggers Receive pattern for 3 pulses ahead Triggering Event Codes Start Beam Kly Standby Event Timestamp, pattern records, and BSA ready Acq Trigger Kly Accel Fiducial Event Received Fiducial B0 F3 18 500 0 1023 Time (usec) 100 0.3

  9. Tallies for 2007 Commissioning • # EVRs = 31 (mostly PMC) • # IOCs with EVRs = 28 • # EVR Fanouts = 4 • # Hardware Triggers = 120 and counting • All TTL except 2 NIM triggers for QDCs • Most require short cables (except LLRF) • EVR with clock not yet available • All acquisition electronics using either internal clocks, clock output from the RF timing system, or other external clocks

  10. Progress since Oct, 2006 • Installation in sector 20 and 21, commissioning in-progress, most timing delays are “iced-in” • Finished hardware bench testing • Finished PMC-EVR driver • EVG sequence RAM programming at 360Hz, conditional logic is primitive but good enough for now • Event pattern records and timestamp distribution on the EVR IOCs • Finished cabling plans and documentation • Finished beam-synchronous acquisition

  11. Trigger Control Display

  12. Trigger Event Assignment Display

  13. EVG Displays

  14. Issues • Outstanding problem (presumably software) where CPU hangs when EVR interrupts are enabled. Some IOCs running without interrupts (hardware triggers but without timestamps, BSA, or event code IRQs). • Documentation and help screens sorely lacking. • EVG IOC doesn’t know when there’s no beam, only when beam is possible – limits trigger conditions. • Software not yet in place to handle hardware and communication errors.

  15. Tasks • Long Haul Fiber Test – next month • BC2 (sectors 21 to 30): • 60 EVRs to order - 34 VME, 26 PMC • 5 fanout modules (1 every 2 sectors) • $250K, needed by August • SW - only DB and display work planned • Still some existing database and display work to do • SLC-aware IOC BPM integration still in progress • Software - fix hang problem, add HW error detection and recovery • Beyond BC2: • New LCLS MPS interface • BSY/LTU/Undulator Procurement and Plans • Changes to EVR firmware to change behavior when multiple triggers on a single pulse • Generic trigger delay scan package • Bunch charge change on pulse-by-pulse basis? • More complex conditional logic for event codes (EVG) and pulse-to-pulse changes in trigger attributes?

  16. Event System – Hardware Status • The New LCLS Event System has been installed in the Injector and S20 • We have successfully integrated it with the SLC Timing System (required some mods to EVG) • The Event System HW is performing as expected • At the first order / Still in its infancy • Other than EVR IRQ Problem / HW working • The Next HW Challenge is Long-Haul Distribution of Timing

  17. Diagram shows IN20 / LI20 Event System installation Top-Level shows connections to SLC Timing, MDL The EVG Crate is shown with its fanouts to all subsystems IN20 Installation

  18. Event System HW: Long-Haul Dist. • For BC2 & beyond, the biggest challenge is Long-Haul distribution of timing data via the Fiber-Optical (F-O) Links • Why? • MRF Event System is designed around Multi-Mode SFP (Small Form-Factor Pluggable) F-O links which allow a maximum fiber length of ~300 meters • Our requirements include runs of several Kilometers (at least) • Cannot daisy-chain the event F-O links: exceeds the jitter budget • Temperature effects on long fibers – drift, but how bad?

  19. Event System HW: Long-Haul Dist. • Proposed Solution: New HW and some testing • Single-Mode, pin-compatible SFP modules are commercially available (Agilent ACFT-57R5) • All us to go ~10KM • Should plug right into our event system HW • Have ordered some, will test when they arrive • Still does not solve temperature-induced phase-drift problem • Propose to solve by either/and: • Running Long Fiber in temperature-controlled environment • Re-Syncing EVRs to a locally-distributed 119MHz source

  20. Event System HW: Special Test Long-Haul Event Fiber System Test: • What it will determine: • Function of Single-Mode SFP Modules • Drift, Trigger time jitter, Phase Noise • How: • Compare two EVR’s triggers & RF Clocks • One EVR Short-Haul • Other EVR Long-Haul • Also compare to reference RF Clock • When: • As soon as possible, have all components except EVRs • New RF-recovery EVRs due in at end of April

  21. Event System – Long-Haul Fiber System Test