1 / 12

RBSP Electric Field and Waves Instrument (EFW)

RBSP Electric Field and Waves Instrument (EFW). Electrical Peer Review DCB Michael Ludlam. Overview. Sept 2nd & 3rd 2009. EFW ELECTRICAL PEER REVIEW. DCB board hosts: the Z80 processor contained in the Actel RTAX FPGA PROM, SRAM and EEPROM program memory.

kasen
Download Presentation

RBSP Electric Field and Waves Instrument (EFW)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. RBSPElectric Field and Waves Instrument(EFW) Electrical Peer Review DCB Michael Ludlam EFW ELECTRICAL PEER REVIEW

  2. Overview Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW • DCB board hosts: • the Z80 processor contained in the Actel RTAX FPGA • PROM, SRAM and EEPROM program memory. • Switched SDRAM TM memory (short term) • Switched FLASH TM memory (long term) • Spacecraft interface using LVDS • Interface with BEB, DFB and PCB (on LVPS) • ADC for digitalization of HK • LDO regulators for 3.3V and 1.5V supplies. 2

  3. Requirements Requirements as listed in the DCB Specification document RBSP_EFW_DCB_003E Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW 2

  4. Schematic & Layout Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW • Flight Schematic RBSP_EFW_DCB_004K • Layout for ETU built to RBSP_EFW_DCB_004G, layout for flight built to RBSP_EFW_DCB_004K • Changes from ETU: • Buffers run as warm spare for the flash, SDRAM. • Removal of filter on regulator supplies (no longer necessary after SEU testing of parts). • Corrected switch to SDRAM and flash • Minor changes to layout to correct layout errors • Added buffer enable control to the flash to FPGA • Changed DIN96 connector to the new KA98 connector. • Added Analog Spare nets to connector for spares. • Differences between ETU and Flight: • FPGA on ETU board is Aldec adaptor board with A3P1500 part. • Oscillator is commercial part. • Other parts are engineering versions of flight parts. • Board will be manufactured from FR4 (4101/26) 2

  5. Grounding Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW Connection from DGND to chassis is close to front plate. Connection from DGND to AGND is at the ADC. 2

  6. Thermal Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW 2

  7. Mass Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW NTE is 667g CBE is 543g CBE includes front panel, connectors, shield, wedgelocks. Staking plan – Single CQFP (FPGA) part needs to be staked carefully, other dual flatpacks will require standard staking. 2

  8. Power Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW 1.8VD    50mA 3.6VD    135mA (SDRAM no FLASH) 5VD    4mA 5VA 15mA  -5VA    10mA 10VA 1mA average. -10VA 0mA average. 2

  9. Radiation Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW • All DCB Active parts are rad hard / rad tolerant or have undergone a TID test. TID requirement is now 13kRad after ray trace analysis. • All DCB Active parts are SEU immune up to 80MeV/cm2 or have a waiver. • Parts with waiver: • LTC1604 (ADC) • Flash memory • Parts on S/C interface have been tested by APL for DDD. No other interface out of IDPU box. 2

  10. ETU Testing Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW • Board has supported FSW, FPGA and IDPU testing. • No modifications have been necessary other than described above. • Still to be done: • Minor tweaks of signal trace impedances. • PCB circuitry checkout 2

  11. Flight Test Plan Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW Short test plan was written for ETU testing. This will be developed into a test procedure for the flight board. Once the board is populated and delivered to UCB functionality that can be checked at a hardware only level will be verified before handing over to FPGA verification and FSW verification. 2

  12. Parts List & Derating Sept 2nd & 3rd 2009 EFW ELECTRICAL PEER REVIEW 2

More Related