Radiation Belt Storm Probes Electric Field and Waves Instrument

1. Radiation Belt Storm ProbesElectric Field and Waves Instrument Digital Fields Board Peer Design Review Wesley D. Cole (Hardware Design Engineer) Laboratory for Atmospheric and Space Physics University of Colorado at Boulder

2. DFB Block Diagram

3. DFB Requirements

4. DFB Requirements

5. EFW Requirements

6. EMFISIS SCM & MAG Requirements

7. General EFW Requirements

8. Changes Since PDR Added second SRAM Removed ADC power switching Modified analog buffer circuits for better transient recovery Increased value of DC blocking capacitor for AC channels to increase bandwidth V#AC (Burst 2) measurement range expanded from ±10 V to ±12.5 V E##AC (Burst 2) measurement range corrected to ±400 mV/m Reworked packets to add EMFISIS Magnetometer back-up capability Solitary Wave Counter defined Added (V1dc + V2dc + V3dc + V4dc) / 4 data product to FFT (SPEC) and FilterBank Changed number of frequency bands in FFT (SPEC and XSPEC) 8

9. EFW – DFB Documentation DFB-IDPU Mechanical ICD (RBSP_IDP_MEC_200RevF) DFB Specification (RBSP_EFW_DFB_001A_SPEC Rev D) AXB and SPB signals (Interface with BEB) Interface with DCB Interface with LVPS Interface through backplane DFB FPGA Specification EFW to EMFISIS Electrical Interface Control Document (RBSP_EFW_to_EMFISIS_ICD_revD.doc) SCM and MAG signals from EMFISIS 9 EFW INST+SOC PDR

10. EFW – DFB Resources Mass and Power Requirements Mass CBE based on measured mass of EM board Power CBE based on measurements plus analysis of current design (i.e. FPGA) Housekeeping Telemetry Requirements DFB produces no analog housekeeping FPGA diagnostic housekeeping sent to ground on request Commanded through DCB 10 EFW INST+SOC PDR

11. Materials & EEE Parts Status • Materials Identification List • Up-to-date • Regular meetings with PMPCB • Need to add PWB data when ordered (will be per required IPC specs) • Fasteners need to be approved • EEE Parts List • Up-to-date • Regular meetings with PMPCB • No issues • Ordering status • 8 on-order (due 11/10/09 at latest) • 2 to be ordered (in process, due mid-December) • 4 to be supplied by UCB • 1 to be supplied by APL (FPGA) 11

12. DFB Thermal Analysis Power Dissipation FPGA: 394 mW LTC1604: 167 mW, Duty Cycle: 0.75 (Active / Nap Mode) FPGA: θJA = 12.3 °C/W LTC1604: θJA = 95 °C/W TJ = TA + (θJA x P) FPGA: TJ = TA + 5 °C (For TA = 65 °C, TJ = 70 °C) LTC1604: TJ = TA + 16 °C (For TA = 65 °C, TJ = 81 °C)

13. DFB Component Derating • Decoupling and Filter Capacitor Voltage Rating: 25 V (± 10 V Max) • Bulk Decoupling (Tantalum) Capacitor Voltage Rating: 10 V (3.3 V Max), 15 V (± 5 V Max), 25 V (± 10 V Max) • Decade Divider Ratings: 100 mW per resistor (46 mW Max), 300 V (± 225 V Max) • DC Blocking Capacitor Voltage Rating: 500 V (± 225 V Max) • Precision Foil Resistor Network Ratings: 200 V (± 10 V Max), 200 mW (3 mW Max) • Transistor Ratings: IC = 600 mA (2 mA Max), VCEO = 50 V (2.5 V Max), VCBO = 60 V (1.9 V Max), PT = 500 mW (5 mW Max), hFE = 35 (10 Max)

14. DFB Parts Concerns • The MSK5822-3.3 voltage regulators may draw up to 500 mA of start up saturation current in addition to the load current. This means that when powering up the DFB’s 3.3 V rail, the LVPS may have to supply approximately 600 mA to the DFB for a few milliseconds while simultaneously meeting the 3.3 V power requirements of the DCB. Does the LVPS have sufficient current resources to meet this requirement? • The MSK5800 start up saturation current draw is several hundred milliamps less. The DFB could use the MSK5800, but its dropout voltage may not meet our requirements.