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Chapter 12 CPU Structure and Function. CPU Sequence. Fetch instructions Interpret instructions Fetch data Process data Write data. CPU With Systems Bus. CPU Internal Structure. Registers. CPU must have some working space (temporary or scratch pad storage) Top level of memory hierarchy

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cpu sequence
CPU Sequence
  • Fetch instructions
  • Interpret instructions
  • Fetch data
  • Process data
  • Write data
  • CPU must have some working space (temporary or scratch pad storage)
  • Top level of memory hierarchy
  • Number and function vary between processor designs
user visible registers
User Visible Registers
  • General Purpose
  • Data
  • Address
  • Control
general purpose registers
General Purpose Registers
  • May be true general purpose

May be used for data or addressing

  • May be restricted
  • Data
    • May include Accumulator
  • Addressing
    • May include Segment Register(s)
general purpose registers design decision
General Purpose Registers Design Decision
  • Make them general purpose ?
    • Increase flexibility and programmer options
    • Increase instruction size & complexity
  • Make them specialized
    • Smaller (faster) instructions
    • Less flexibility
how many gp registers
How Many GP Registers?
  • Between 8 – 32 ?
  • Fewer = more memory references
  • More does not tend to reduce memory references and takes up processor real estate
how big
How big?
  • Large enough to hold full address
  • Large enough to hold full word

- Sometimes possible to combine two data registers

control status registers
Control & Status Registers
  • Program Counter
  • Instruction Decoding Register
  • Memory Address Register
  • Memory Buffer Register
  • Program Status Word
control condition code registers
Control - Condition Code Registers
  • CC: Sets of individual bits
    • e.g. result of last operation was zero
  • Can be read (implicitly) by programs
    • e.g. Jump if zero
  • Usually can not be set by programs
program status word
Program Status Word
  • A set of status and/or control bits
  • Includes Condition Codes
  • Priority, Interrupt enable/disable
  • Supervisor State information

- Kernel Mode - Not available to user programs

(Used by operating system)

(Allows privileged instructions to execute)

other registers
Other Registers
  • May have registers pointing to:
    • Process control blocks
    • Interrupt Vectors
  • Note: CPU design and operating system design are closely linked
instruction cycle with indirect
Instruction Cycle with Indirect

Note: ‘Indirect’ allows for fetching data with indirect addressing

data flow instruction fetch
Data Flow (Instruction Fetch)
  • Fetch
    • PC contains address of next instruction
    • Address moved to MAR
    • Address placed on address bus
    • Control unit requests memory read
    • Result placed on data bus, copied to MBR, then to IR
    • Meanwhile PC incremented by 1 (or more)
data flow data fetch
Data Flow (Data Fetch)
  • IR is examined
  • If indirect addressing, indirect cycle is performed
    • N bits of MBR transferred to MAR
    • Control unit requests memory read
    • Result (address of operand) moved to MBR
data flow execute
Data Flow (Execute)
  • May take many forms
  • Depends on instruction being executed
  • May include
    • Memory read/write
    • Input/Output
    • Register transfers
    • ALU operations
data flow data store
Data Flow (Data Store)
  • If indirect addressing, indirect cycle is performed
    • N bits of MBR transferred to MAR
    • Control unit requests memory read
    • Result (address of operand) moved to MBR
data flow interrupt
Data Flow (Interrupt)
  • Context Stored / Interrupt Acknowledged
  • Vector Fetched & Intr Serv Routine Addr => PC
  • Intr Serv Routine (Handler) executed
  • ….
  • Context Restored
  • Continue execution of main program

Consider the instruction sequence as:

  • Fetch instruction
  • Execution instruction (often does not access main memory)

Can computer fetch next instruction during execution of current instruction ?

  • Called instruction Prefetch

What are the implications of Prefetch?

improved performance with prefetch
Improved Performance with Prefetch
  • Improved but not doubled:
    • Fetch usually shorter than execution
    • Any jump or branch means that prefetched instructions are not the required instructions
  • Could we Prefetch more than one instruction ?
  • Could we add “more stages” to improve performance even more?
  • This is Pipelining

Consider the instruction sequence as:

  • instruction fetch,
  • decode instruction,
  • fetch data,
  • execute instruction,
  • store result,
  • check for interrupt

Consider it as an “assembly line” of operations.

Then we can begin the next instruction assembly line sequence

before the last has finished. Actually we can fetch the next

instruction while the present one is being decoded.

This is pipelining.

define pipeline stations
Define Pipeline “stations”
  • Fetch instruction (FI)
  • Decode Instruction (DI)
  • Calculate Operand Addresses (CO)
  • Fetch Operands (FO)
  • Execute Instruction (EI)
  • Write Operand (WO)

Let’s define some possible Pipeline stations:

the effect of a conditional branch on instruction pipeline operation
The Effect of a Conditional Branch on Instruction Pipeline Operation

Instruction 3 is a conditional branch to instruction 15:

alternative pipeline depiction
Alternative Pipeline Depiction

Instruction 3 is conditional branch to instruction 15:

dealing with branches possible approaches
Dealing with Branches – Possible approaches
  • Multiple Streams
  • Prefetch Branch Target
  • Loop Buffer
  • Branch Prediction
  • Delayed Branching
multiple streams
Multiple Streams
  • Have two pipelines
  • Prefetch each branch into a separate pipeline
  • Use appropriate pipeline


  • Leads to bus & register contention
  • Multiple branches lead to further pipelines being needed
prefetch branch target
Prefetch Branch Target
  • Target of branch is prefetched in addition to instructions following branch
  • Keep target until branch is executed
  • Used by IBM 360/91
loop buffer
Loop Buffer
  • Use Very fast memory (“Loop Buffer Cache”)
  • Maintained by fetch stage of pipeline
  • Check buffer before fetching from memory
  • Very good for small loops or jumps in small code sections
  • Used by CRAY-1
branch prediction
Branch Prediction
  • Predict branch never taken
  • Predict branch always taken
  • Predict by opcode
  • Predict branch taken/not taken switch
  • Maintain branch history table
predict branch taken not taken
Predict Branch Taken / Not taken
  • Predict never taken
    • Assume that jump will not happen
    • Always fetch next instruction
    • 68020 & VAX 11/780, VAX will not prefetch after branch if a page fault would result (O/S v CPU design)
  • Predict always taken
    • Assume that jump will happen
    • Always fetch target instruction

Which is better?

branch prediction by opcode switch
Branch Prediction by Opcode / Switch
  • Predict by Opcode
    • Some instructions are more likely to result in a jump than others
    • Can get up to 75% success with this stategy
  • Taken/Not taken switch
    • Based on previous history
    • Good for loops
    • Perhaps good to match programmer style
maintain branch table
Maintain Branch Table
  • Perhaps a cache table of three entries:

- Address of branch

- History of branching

- Targets of branch

intel 80486 pipelining
Intel 80486 Pipelining
  • Fetch (Fetch)
    • From cache or external memory
    • Put in one of two 16-byte prefetch buffers
    • Fill buffer with new data as soon as old data consumed
    • Average 5 instructions fetched per load
    • Independent of other stages to keep buffers full
  • Decode stage 1 (D1)
    • Opcode & address-mode info
    • At most first 3 bytes of instruction
    • Can direct D2 stage to get rest of instruction
  • Decode stage 2 (D2)
    • Expand opcode into control signals
    • Computation of complex address modes
  • Execute (EX)
    • ALU operations, cache access, register update
  • Writeback (WB)
    • Update registers & flags
    • Results sent to cache & bus interface write buffers