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ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs

ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs. Dr. Konstantinos Tatas com.tk@fit.ac.cy http://staff.fit.ac.cy/com.tk. ACOE201 Laboratory Structure and Objectives. Small group experiments lasting approximately two periods Lab report

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ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs

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  1. ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy http://staff.fit.ac.cy/com.tk

  2. ACOE201 Laboratory Structure and Objectives • Small group experiments lasting approximately two periods • Lab report • Design and implementation of a simple CPU • Hardware: Xilinx Spartan-3E Starter Kit • Software: Xilinx ISE • Objectives: • Develop practical digital design skills • Reinforce Computer Architecture concepts by designing and verifying a simple CPU

  3. Xilinx Spartan-3E Starter Kit FPGA LEDs buttons switches

  4. FPGA Principles • A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be configured by the user to emulate any digital circuit as long as there are enough resources • An FPGA can be seen as an array of Configurable Logic Blocks (CLBs) connected through programmable interconnect (Switch Boxes)

  5. FPGA structure

  6. Simplified CLB Structure

  7. Example: 4-input AND gate

  8. Example 2: Find the configuration bits for the following circuit

  9. Interconnection Network

  10. Example 3 • Determine the configuration bits for the following circuit implementation in a 2x2 FPGA, with I/O constraints as shown in the following figure. Assume 2-input LUTs in each CLB.

  11. CLBs required

  12. Placement: Select CLBs

  13. Routing: Select path

  14. Configuration Bitstream • The configuration bitstream must include ALL CLBs and SBs, even unused ones • CLB0: 00011 • CLB1: 01100 • CLB2: XXXXX • CLB3: ????? • SB0: 000000 • SB1: 000010 • SB2: 000000 • SB3: 000000 • SB4: 000001

  15. Realistic FPGA CLB: Xilinx

  16. FPGA EDA Tools • Must provide a design environment based on digital design concepts and components (gates, flip-flops, MUXs, etc.) • Must hide the complexities of placement, routing and bitstream generation from the user. Manual placement, routing and bitstream generation is infeasible for practical FPGA array sizes and circuit complexities.

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