EE/MatE167 Tape Out Day Celebration

1. EE/MatE167 Tape Out Day Celebration Spring 2003 A Brief history of SJSU’s IC deign Fabricate and Test Curriculum EE/MateE 167

2. Agenda • The way we were. • What happened this semester. • What to improve. EE/MateE 167

3. The way we were (1999) • The only course in which any IC was fabricated was EE/MatE129. • Used a 5 mask pmos process • While a robust process it was too hard to do in one semester, and it did not use available techniques to reduce fixed oxide charge • This made it impossible to make a normally off nmos transistor which would only require 4 masks. • Students did no real IC design. • EE 166 was a complete waste of time. EE/MateE 167

4. The way we were (2000) • A senior design project is started in the fall to reduce fixed oxide charge due to oxidation, and mobile oxide charge due to sodium contamination. • Ultimately fixed oxide charge is reduced: • Our RCA cleaning process is a result. • Post Oxide Anneal is also used. • Annealing the MOS capacitors in Forming gas is also adopted • A new 129 nmos,4-mask process is developed (MSE project). • Short Channel effects reduce VT, but the class is much easier to teach and take. EE/MateE 167

5. The way we were (2001) • EE/MatE 167 is offered for the first time (5 Students)! • Eric Basham get frustrated with the fact that: • I was writing the traveler hours before we needed to do a process. • The Athena deck was not finished before we started processing. • The mask was deigned 100% by DP • The statistics part of 167 was disconnected with he processing part. • We get PMOS device to work! • An incorrect annealing step fails to activate the As so not nmos. • Neil broke the wafers as we tried to re-sputter them, after proper anneal. EE/MateE 167

6. The way we were (2001) • EE166 is offered for the first time as a course that: • Uses cadence tools a a real design flow to design a CMOS IC. • Students used a a stepping stone to MOSIS based projects for senior design. • Students design ALU’s to be included on the spring run on 167. • EE129 offered in the fall for first time • New mask set • Contact resistance problems? EE/MateE 167

7. The way we were (2002) • EE/MatE 167 is offered for the second time (10 Students)! • NMOS, PMOS, LDMOS devices created! • We find out that our alignment error causes our larger circuits to fail. • ESD protection fails as well and an eighth mask is required to get anything to work. • The statistics part of 167 was disconnected with he processing part. • Mask designed 80% by DP • EE166 Improved • .5 microns features used • New tutorials • EE129 • Contact resistance problems?, VT problems? EE/MateE 167

8. The way we were (2002) • Four circuits are sent to Mosis fabrication, 2 are tested! EE/MateE 167

9. 4-BIT ALUFabricated by MOSIS EE/MateE 167

10. 4 BIT ALU Design EE/MateE 167

11. 4 BIT ALU Fabricated in Lab EE/MateE 167

12. LDMOS EE/MateE 167

13. Spring 2003 • What happened? • Based on statistics, new design rules are implemented. • Gate Array Designed! • Analog Leaf Cell Designed! • The mask is 95% designed by students! • Lab is down so all work is done at Stanford. EE/MateE 167

14. Spring 2003 • What happened? • Gate Array: • With out a real design flow in place or tested the following circuits were designed and taped out. • ALU standard • ALU AOI • A/D • DFF • Library • Analog Leaf Cell: • Current Mirror • Opamp1 • Opamp2 • Class A/B amplifier EE/MateE 167

15. Spring 2003 • What else happened? • LDMOS improved • CCD filters added • Transconductor added • MEMS Structures added • We still have to finish fabrication and do some testing. • Statistics are still disconnected from lab. EE/MateE 167

16. You should all be very proud of yourselves! Tape out day is the most stressful thing in the world! Eric and I am proud to know you! EE/MateE 167

17. Problems • VT RS and RC problems in 129 EE/MateE 167

18. Improvements • Do IC design first! • Then Athena • Then Testing • Then Solar cell? EE/MateE 167

19. Improvements • ? • ? • ? • ? • ? • ? • ? EE/MateE 167