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Spectral Analysis for BIST Synthesis in Sequential Circuit

This paper proposes a method for BIST synthesis in sequential circuits using spectral analysis. The method involves analyzing sequential vectors in the spectral domain and implementing significant spectral components for BIST. Results show increased fault coverage and reduced area overhead compared to traditional methods.

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Spectral Analysis for BIST Synthesis in Sequential Circuit

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  1. Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, Alabama 36849, USA Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  2. Outline • Specifying a BIST problem • Proposed method • Spectral Analysis • BIST implementation • Results • Fault Coverage • Area Overhead • Conclusion Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  3. Two Types of BIST methods • Scan-based testing • Advantages: • High fault coverage • Disadvantages: • Area & delay overhead, yield loss, large vector size and testing times • Non-scan based testing • Advantages: • Disadvantages of scan-based testing eliminated • Disadvantages: • Requires sequential ATPG • High test generation complexity and low fault coverages • Alleviated using DFT schemes • Sequential ATPG-like vector generation in BIST environment Problem definition Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  4. Proposed Method • Step 1: Spectral analysis • Sequential vectors (ATPG or any other type) analyzed in the spectral domain • Significant spectral components chosen for BIST implementation • Step 2: BIST implementation • Hardware synthesis of significant spectral components to generate ATPG-like vectors Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  5. Test vectors and bit-streams Sequential Circuit (CUT) Outputs Input J Input 3 Input 5 Input 1 Input 4 Input 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 → A bit-stream Time . . . . . . . . . . . . . . . . . . . . . . . . . . . Vector K→ Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  6. Spectral Characterization of a Bit-Stream w0 • Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream • Walsh functions form the rows of a Hadamard matrix w1 w2 w3 H8 = 1 1 1 1 1 1 1 1 1 -1 1 -1 1 -1 1 -1 1 1 -1 -1 1 1 -1 -1 1 -1 -1 1 1 -1 -1 1 1 1 1 1 -1 -1 -1 -1 1 -1 1 -1 -1 1 -1 1 1 1 -1 -1 -1 -1 1 1 1 -1 -1 1 -1 1 1 -1 Walsh functions (order 8) w4 w5 w6 w7 Example of Hadamard matrix of order 8 time Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  7. Analyzing Bit-Streams of ATPG vectors Input 1 Input 2 . . . Set 1 Vector 1 Vector 2 . . . Spectral coeffs. Bit stream Spectral Analysis 0s to -1s Set j Time . . . . . . . . . . C(2,1) input 2 set 1 input 2 set 1 Sets of bit-streams of Input 2 Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  8. Determining Significant Components For input i Averaged Spectrums . . . . Set J Set 1 Averaging Component Spectrum . . . . Phases of significant components Averaging Power Spectrum . . . . M significantcomponents chosen Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  9. Input Vector Holding • Hold input vectors constant while applying system clock. • Holding length related to sequential depth. • Sequential depth: Maximum number of FFs on any path between PI and PO. • Holding a vector constant for number of clock cycles equal to sequential depth propagates a fault through the activated sequential path[1]. • Holding maps combinational ATPG onto acyclic sequential circuit [2]. • However, all testable combinational ATPG faults not detected by holding [3]. [1] L. Nachman, K. Saluja, S. Upadyaya, and R. Reuse, “Random Pattern Testing for Sequential Circuits Revisited,” in Proc. Fault-Tolerant Computing Symp., pp. 44–52, June 1996. [2] H. B. Min and W. A. Rogers, “A Test Methodology for Finite State Machines using Partial Scan Design,” J. Electronic Testing: Theory and Applications, vol. 3, no. 2, pp. 127–137, 1992. [3] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, "Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits," IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, vol. 24, no.6, pp. 948-956, June 2005. Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  10. Holding and Weighted Random Patterns Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  11. Weighted random bit-stream (W=0.5) Weighted random bit-stream (W=0.5) Bit-stream of spectral component Noise inserted bit-stream Proportion: SC1 = 0.5 SC2 = 0.5 SC1 Proportion: SC1 = 0.25 SC2 = 0.25 SC3 = 0.5 Weighted random bit-stream (W = 0.25) SC2 SC3 BIST Architecture M-bit counter divides system clock frequency repeatedly by 2 and generates BIST clock System clock To CUT Clock divider and holding circuit Cellular Automata Register with AND-OR gates N-bit counter with XOR gates BIST clock Hadamard wave generator Weighted pseudo-random pattern generator 2 Spectral component synthesizer Input 1 System clock 3 BIST clock To CUT 1 Input 2 Randomizer 1 Hadamard Components Input 3 1 Weighted pseudo-random bit-streams Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  12. Equal or more faults detected than ATPG in5 / 8 circuits Equal or more faults detected than ATPG in5 / 8 circuits Hadamard BIST Results 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  13. Hadamard BIST Results Maximum faults detected in 6 / 8 circuits Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  14. Longer BIST Sequences ATPG fault coverage achieved in 6 / 8 circuits Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  15. Area Overhead Approximately similar area overheads 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  16. Conclusion • Proposed a novel method for test generation for sequential circuit BIST • Proposed unique circuits for mixing spectral components and noise • Method detects equal or more faults than ATPG vectors in 6 out of 8 ISCAS’89 benchmark circuits • Moderate area overhead compared to existing methods • Proposed method is flexible and adaptable • Any other suitable vectors can be used instead of ATPG vectors. • Any compatible transform for binary bit-streams can be used for spectral analysis instead of Hadamard transform. • BIST coverage limited by coverage of ATPG vectors • DFT for sequential circuits to improve ATPG coverage Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

  17. Thank You!Any questions please ? Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan

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