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Crossing-Free Boundary Labeling Using Hyperleaders

Crossing-Free Boundary Labeling Using Hyperleaders. Chun-Cheng Lin Taipei Municipal University of Education. Outline. Introduction Motivations Our results One-side case  O(n log n) time solvable Two-side case  O(n 2 ) time solvable Four-side case  simulated annealing

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Crossing-Free Boundary Labeling Using Hyperleaders

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  1. Crossing-FreeBoundary LabelingUsing Hyperleaders Chun-Cheng Lin Taipei Municipal University of Education

  2. Outline • Introduction • Motivations • Our results • One-side case  O(n log n) time solvable • Two-side case  O(n2) time solvable • Four-side case  simulated annealing • Conclusion & Future work

  3. Point features • e.g., city • Line features • e.g., river • Area features • e.g., mountain Map Labeling

  4. Type-opo leaders • Type-po leders • Type-s leaders (Bekos & Symvonis, GD 2005) Boundary Labeling [Bekos et al., GD 2004] label site leader 1-side, 2-side, 4-side Min (total leader length) s.t. #(leader crossing) = 0

  5. Polygons labeling Multi-stack boundary labeling Variants • Type-od leader • Type-pd leader • Type-do leader 5

  6. Legend: Brown booby Taiwan hill partridge Masked palm civet Hawk Melogale moschata Bamboo partridge Chinese pangolin Mallard Many-Site-to-One-Label Boundary Labeling(a.k.a., Many-to-One Boundary Labeling)(Lin, Kao Yen, 2008) Brown booby Distribution of some animals in Taiwan: Taiwan hill partridge Masked palm civet Hawk Melogale moschata Bamboo partridge Chinese pangolin Mallard

  7. Brown booby Taiwan hill partridge Masked palm civet Melogale moschata Hawk Bamboo partridge Chinese pangolin Mallard Two-Side Many-to-One Boundary Labeling

  8. PS2 Port 8 DIMMs USB Port ATX Power Supply COM Port 2 LAN Ports VGA Port Battery 4 CPUs BIOS 6 Expansion Slots 2 Chipsets IDE Slot 6 SATA Connectors One More Example– Server Motherboard –

  9. Track Routing Area l1 hyper-leader l2 R Many-to-One Boundary LabelingUsing Hyperleaders & Dummy Labels • Type-opo hyperleaders & dummy labels • Main features • No confusion and crossings between leaders • Suitable for labeling the sites with clusters • One-side and two-side cases are suitable for the maps with vertical-strip shapes Track Routing Area adding dummy labels l1 l2 dummy label R l1’ No leader crossings

  10. Our Concerned Problem • Minimizing the number of dummy labels s.t. there are no leader crossings. Furthermore, after determining # & pos of dummy labels, the number of bends is minimized; the total leader length is minimized. R

  11. Our Theoretical Results for Many-to-One Boundary Labeling Note that c is a number depending on the sum of edge weights.

  12. One-Side Case Observation. Only the order of y-coordinates of sites matters. Input Step 1. Step 2. Step 3. l1 l2 l3 l4 l5 l6 l7 l8 g1 g1 g2 g2 g4 g4 g3 g3 g5 g5 g6 g6 g7 g7 g8 g8 R R R R

  13. How to Route Hyperleaders?  gi gi Push i to stack S. (the routing of gi is determined after the routing of gi+1 is determined) li li yp(li) li+1 li+1 R R   gi gi li li gi gi yp(li) yp(li) li li li+1 li+1 R R R R    li-1 li-1 li-1 li-1 li li li yp(li) li yp(li) gi gi gi gi R R R R

  14. Two-Side Case Step 1. Step 2. g1 g2 its recently shown guy. g3 g4 L R g5 g6 g7 g8 the concerned label R Scan from the top to the bottom. Each label is placed on the right or the left line. If moving labels in L to R does not result in any dummy label, the concerned label is placed on the same line as its guy; o.w. ... 14

  15. R An Example Make the numbers of components on both sides as equal as possible Move to the same side of its recently shown guy, if no crossing.

  16. R An Example (cont.)

  17. 2 CPUs PS2 Port 6 DIMMs COM Port PS2 Port 8 DIMMs VGA Port 2 LAN Ports 6 Expansion 6 DIMMs USB Port ATX Power Supply IDE Slot 2 CPUs COM Port 2 LAN Ports 2 DIMMs VGA Port Battery ATX Power Supply 4 CPUs BIOS Battery 6 Expansion 2 Chipsets BIOS IDE Slot 2 Chipsets 6 SATA 6 SATA Many-to-One Boundary Labeling • The original • New

  18. Our Results * Note that n is the number of sites.

  19. Four-side case • [Bekos et al., 2007] • Determining which sites are connected to one of the four sides so that the objective is achieved leads to the NP-hard Partition problem • Use the simulated annealing (SA) to solve the four-side case

  20. A4 A2 A1 p A3 Simulated Annealing for 4-side case • Configuration • Corresponded to a site p • Site p divides the map into four regions A1-A4 • Initial configuration • A configuration where the sites in each region are as equal as possible • Neighbor • Randomly select a corner c of the map • Rotate the line connected to c around c in counterclockwise direction • The configuration corresponding to the first scanned site is selected as the neighbor • Energy cost function = • The cooling schedule is based on the previous work p c  (normalized # of dummy labels) + (1-)(normalized total leader length)

  21. Statistics

  22. Experimental Results (I) 22

  23. Experimental Results (II) 23

  24. A Practical Example

  25. 2 CPUs PS2 Port 6 DIMMs COM Port VGA Port 2 LAN Ports 6 Expansion 6 DIMMs IDE Slot 2 CPUs 2 DIMMs ATX Power Supply Battery BIOS 2 Chipsets 6 SATA Conclusion • Crossing-free many-to-one boundary labeling using hyperleaders (and dummy labels) • 1-side case  O(n log n) time for dummy label min. problem • 2-side case  O(n2) time for dummy label min. problem • 4-side case  simulated annealing

  26. Future work • Considering other kinds of leaders l1 l1 l1 l2 l2 l2 l3 l3 l3 l4 l4 l4 R R R l5 l5 l5 Steiner points Steiner Tree MST

  27. Thank you for your attention!

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