Claudio Piemonte a , Maurizio Boscardin a , Alberto Pozza a , Sabina

1. First electrical characterization of 3D detectors with electrodes of the same doping type Claudio Piemontea, Maurizio Boscardina, Alberto Pozzaa, Sabina Ronchina, Nicola Zorzia, Gian-Franco Dalla Bettab, Luciano Bosisioc \ a ITC-irst, Microsystems Division, via Sommarive 18, 38050 Povo di Trento, Italy b University of Trento, DIT, Trento, Italy c Physics Department, University of Trieste and INFN, Trieste, Italy RD50 workshop

2. Outline • Single-Type Column 3D detector concept • Fabrication of 3D-STC detectors • Layout and preliminary electrical results • Conclusions

3. ionizing particle cross-section between two electrodes n+ n+ holes drift in the central region and diffuse towards p+ contact electrons are swept away by the transversal field STC-3D detectors - concept (1) [C. Piemonte et al, Nucl. Instr. Meth. A 541 (2005)] Sketch of the detector: Functioning: n+-columns p-type substrate grid-like bulk contact Adv. over standard 3D: etching and column doping performed only once

4. n+ electrodes p-type substrate Uniform p+ layer 3DSTC detectors - concept (2) Further simplification: holes not etched all through the wafer No need of support wafer. Bulk contact is provided by a backside uniform p+ implant single side process.

5. 50mm 0V -5V 300mm -10V -15V 3DSTC detectors - 3D simulations Potential distribution (horizontal cross-section) Potential distribution (vertical cross-section) null field regions • Drawbacks: • once full depletion is reached it is not possible • to increase the electric field between the columns • large low field region Both can be improved using higher substrate doping concentration

6. 10 m Hole depth: 120μm Fabrication process (1) MAIN STEPS: 1. Hole etching withDeep RIE machine (step performed at CNM, Barcelona, Spain) 2. n+ diffusion (column doping) 3. passivation of holes with oxide 4. contact opening 5. metallization metal oxide hole contact n+ diffusion • CHOICES FOR THIS PRODUCTION: • No hole filling (with polysilicon) • Holes are not etched all through the wafer • Bulk contact provided by a uniform p+ implant

7. FZ (500 m) resistivity > 5.0 k cm • Cz (300m) resistivity > 1.8 k cm Fabrication process (2) • Substrates used for this production: Si High Resistivity, p-type, <100> • Surface isolation: • p-stop • p-spray • Sintering • Standard @ 420˚C for FZ • 380˚C for Cz to minimize thermal donor activation

8. Mask layout “Large” strip-like detectors Small version of strip detectors Planar and 3D test structures “Low density layout” to increase mechanical robustness of the wafer

9. High variation due to different substrates Ileak measured below full depletion due to Vbreak 50 - 60 Planar test structures measurements Standard planar test structures Electrical parameters compatible with standard planar processes

10. Single hole p-stop p-stop around the entire region 3D diode – layout: Guard ring 10x10 holes matrix p-stop Bulk • Different 3D-diode layouts: • Different isolation geometry (p-stop) • Different column connections • Different inter-colum distances (ranging from 80μm to 100μm)

11. p-stops Guard ring (n+) - - e- layer Depletion region • diode • guard ring • diode • guard ring • diode • guard ring Vback High field region p-spray Guard ring (n+) Vback Depletion region 3D diode – IV measurements: p-stop case 2nd punch through 1st punch through Ileak = 0.68 ± 0.2 pA/column @ 20V p-spray case Breakdown Ileak = 0.59 ± 0.12 pA/column @ 20V

12. 12 2.50 10 2.00 8 ] -2 Back 1.50 Cdiode [pF] 6 [pF -2 4 C 1.00 2 0.50 0 0.00 0 10 20 30 40 50 60 Vbias [V] 0 10 20 30 40 50 60 Vbias [V] 3D diode – CV measurements (preliminary) Capacitance measurement versus back on a 300μm thick wafer with ~150mm deep columns, 100mm picth Cd 1 2 • region between col. • is not fully depleted • large capacitance full dep. between columns ~ 7V f=10kHz Cd [pF] Phase 1 • region between col. • is fully depleted • depletion proceeds only towards the back (almost like a planar diode) full depletion ~40V depletion width of ~150mm Phase 2 1/Cd2 [pF-2] 1/C2

13. Strip detectors - layout Inner guard ring (bias line) metal p-stop hole Contact opening n+

14. AC coupling: • DC coupling: Punch-through structures DC pads Strip detectors – layout: • Different strip-detector layouts: • Number of columns ranging from 12000 to 15000 • Inter-columns pitch 80-100 m • Holes Ø 6 or 10 m • Two different p-stop layouts: Common p-stop for each strip Single p-stop for each hole

15. p-stop p-spray 30 25 20 Detectors count 15 10 Bias line Guard ring 5 0 >50 0 5 25 30 35 10 15 20 40 45 50 I bias line [nA] Strip detectors – IV measurements: Average leakage current per column < 1pA Number of columns per detector: 12000 - 15000 Current distribution @ 40V of 70 different devices Leakage current < 1pA/column in most of the detectors Good process yield

16. Conclusion • The first production has proved: • The feasibility of 3D-stc detectors • Low leakage currents (< 1pA/column) • Breakdown @ 50V for p-spray and >100V for p-stop structures • Good process yield(typical detector current < 1pA/column) • Samples have been given to: • Glasgow (UK): CCE measurements with a, b, g on 3D diodes • SCIPP(USA): CCE measurements on large strips

17. Na=1e131/cm3 Na=5e121/cm3 Na=1e121/cm3 3D-stc TCAD simulations Simulation of the electric field along a cut-line from the electrode to the center of the cell DRAWBACK: 3D-stc: once full depletion is reached it is not possible to increase the electric field between the columns Maximum electric field depends on substrate doping