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Engineering issues for FPCCD VTX Detector

Engineering issues for FPCCD VTX Detector. Y. Sugimoto KEK July 24, 2007. FPCCD. 5 m m pixel size, 15 m m epi-layer Accumulate signal during a train and read out between trains Moderate readout speed ~10Mpix/s No power cycling

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Engineering issues for FPCCD VTX Detector

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  1. Engineering issues for FPCCD VTX Detector Y. Sugimoto KEK July 24, 2007

  2. FPCCD • 5mm pixel size, 15mm epi-layer • Accumulate signal during a train and read out between trains • Moderate readout speed ~10Mpix/s • No power cycling • Two wafers make a doublet, and three doublets make the detector • Operate at low temperature ~220K ladders are put inside a cryostat

  3. Readout channels • One readout channel covers 128x13000(L1-L2)/128x20000(L3-L6) pixels • For outer layers, larger pixel size may be acceptable and could be 128x13000

  4. Engineering challenge • Power consumption and cooling method • Wafer thinning and the ladder design • Installation method • …. • …. • ….

  5. Power consumption • Heat source • Ohmic loss in gate electrode (probably negligible) • CCD source follower and load resister • Readout ASIC • Clock driver • CCD and ASIC must be inside the cryostat • Clock driver may be put outside the cryostat • Most of power is consumed by “drivers” • No heat source in the image area Our R&D goal: Electronics: < 100 W in the cryostat Mechanics: Compatible with 100W

  6. Power consumption • R&D status • Sensor R&D • First custom CCD in FY2007 • 4ch/chip, 4 different source follower designs • Smallest power consuming channel: ~10mW/ch • Readout ASIC • Amp, CDS, and charge-sharing SAR ADC • Design completed, submission in September • 4ch/chip • < 10mW/ch if output is not connected (driving 100W load with 1V pulse consumes ~10mW!)

  7. Wafer thinning • Two methods are considered • Partial thinning by etching (like DEPFET collab) • Easy to handle • More material (thick frame) • Total thinning by etching or mechanical method • Less material • Hard to handle (wire bonding OK?) • Flatness ?

  8. Partial thinning • Sample CCDs; Front side processed • 300mm thick frame and 20mm thick image area • Flatness is poor  20mm looks too thin

  9. FEA of Ladders Epoxy RVC (Reticulated Vitreous Carbon) Si (CCD wafer) 10 cm Deformation by self-weight is calculated by FEA program COMSOL

  10. FEA of Ladders • Parameters (assumption) • Geometry 0.08%X0/layer

  11. FEA of Ladders • Results • Maximum deformation: • Without gap : vmax=0.536 mm • With 0.2mm gap : vmax=0.723 mm • For longer ladders • vmax ~ l4 ~8.6 mm for 20cm ladder without gap

  12. Summary and future prospect • Among many engineering issues to be studied for FPCCD vertex detector, we have started study for • Power consumption (sensor/ASIC R&D) • Wafer thinning and ladder design • Due to lack of resources, these studies are at very primitive stage • As a long term goal (~2012?), construction of a full size engineering model (dummy detector) would be necessary

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