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Sensor design and mass test system development

Sensor design and mass test system development. Y. Kwon (Yonsei Univ.). F irst real scale prototype chip from CERN. Our involvement. Participation in chip design Preparation of mass test system. Chip design. Chip design opportunities. Interesting approach based on CIS technology

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Sensor design and mass test system development

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  1. Sensor design and mass test system development Y. Kwon (Yonsei Univ.)

  2. Firstreal scale prototype chip from CERN

  3. Our involvement • Participation in chip design • Preparation of mass test system

  4. Chip design

  5. Chip design opportunities • Interesting approach based on CIS technology • Joint efforts with Prof. M. K. Song @ Dongguk Univ. • 2013-2014 : two master degree course students • 2014-2015 : two doctorate degree course students • Student 1 : Daehyeok Kim • Continuation from 2013 • Involvement in front end development • Student 2 : Sungjoo Lee • New involvement • Past experiences in analog/digital circuits.

  6. Front end under study

  7. Interesting features

  8. Mass test system

  9. Issue for the mass test system • 50k delicate pixel sensors • Test configuration • Probe card • Chuck • Test definition : Laser, readout • Automation (machine vision + robot, commercial solution available) • To pick chips from tray, • load them on chuck, • test them according to the test configuration, • and return to the holder. Minimum system to do custom chip test.

  10. Probe-card

  11. PAD layout Total 103 pads to make contact

  12. Task 1, probe card CPU FPGA ETHERNET

  13. Specification 0. Dual pins for each pad Pin A for external connection (power/ground/IO), Pin B to check pin contact with the pad 1. 103 x 2 = 206 pins. 2. 14 + 3 relays as switches when we decouple pin A and pin B 3. 8 LEDs to check probe card position by eye. 4. Contact status check at every 10 ms. 5. Contact status report by ethernet.

  14. PAD size We want dual pin contact for each pad.

  15. Probe needlelayout Invisible Chip

  16. Programming option • Computer + ethernet • Slow, but flexible • On-board CPU • In-between • FPGA • Fast, but limited

  17. Pin A Pin B Input

  18. Algorithm to check contact Disconnect power/input using relay. Send 1.8(V) logicpulse to each digital input pad via pin A and read pin B. If no pair read back, raise chuck via . If any pair reads back, 3. Start careful adjustment ’. 4. Send 1.8(V) sequential logic pulse to other digital input pad via pin A and read pin B. Raise ’ up until all input pad pairs read back. Send 1.8(V) sequential logic pulse to digital input pads via pin A and read pin B. (We will skip step 6 if we worry damage by electrical shock).

  19. 7. Raise ’ up until all input pad pairs read back. 8. FPGA pull down for power pin B, FPGA pull up for ground pin B. 9. Disconnect FPGA output for pin A. 10. Connect power. 11. Check FPGA pin status 12. Raise ’ up until all pin B status is OK. 13. Disconnect pin B for analog input. Use LED to display current status properly. FPGA flexibility enables variation of algorithm.

  20. Chuck

  21. Transparent chuck? Suction control One hole Would sensor be flat on the chuck?

  22. Problem Sensor Chuck Vacuum hole Chuck

  23. Solution More small holes, air-tight chuck

  24. Chucks in preparation We are evaluating the optimal configuration.

  25. Test definition : Laser, readout

  26. Test definition? • Basic elements are ready. • Open chuck in page 24 • Laser (1000-1100 nm)? • X-Y stage with optical mask • Requires further communication with CERN

  27. Status • Optimization in progress with the delivery of proto type sensor. • R&D in coordination with CERN --- We exchange experiences.

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