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Application of Group Delay Equalisation in Testing Fully Balanced OTA-C Filters

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  1. Bashir Al-Hashimi Reuben Wilcock bmah@ecs.soton.ac.uk rw01r@ecs.soton.ac.uk Application of Group Delay Equalisation in Testing Fully Balanced OTA-C Filters

  2. Outline • Introduction • Defect oriented testing • Design of fully balanced OTA-C filter • Fault models and simulation in filter • Proposed test methodology • Test circuitry design • Results • Conclusions

  3. Introduction • Integrated Circuits are subject to defects • Testing is clearly necessary • BIST increasingly attractive for complex IC’s • Many analog BIST schemes in the literature: • Analog scan path approach [Wey, I&M ’90] • Time Domain BIST [Provost et al, GLS ’98] • Current mode approach [Lee et al, CAS-II ’99] • Reconfigurable SC biquad [Cota et al, DATE ’00] • Ramp stimuli based BIST [Nadal et al, DATE ’01]

  4. Design Circuit Simulate with Faults Develop BIST Defect oriented testing • Manufacturing process defects are the major cause of yield loss in ICs [Vinnakota et al] • Short and open faults known as ‘hard faults’ • Simple defect oriented tests can give high fault coverage for common faults [Xing, ITC ’98] • Study fault affects in detail to aid BIST design

  5. gm gm gm gm gm gm gm gm gm gm gm gm gm gm gm Filter Design • Simulated LC ladder fully-balanced OTA-C filter • Low sensitivity to component variations • Symmetrical, differential design rejects noise • Only grounded capacitors • No sampling effects

  6. vdd vdd vdd vdd Vin- Iout+ vdd vdd - + vss vss vss vss gm - + vss vss Vin+ Iout- Fault Models • Select T-level OTA [Nauta, Electronic Letters, ’89] • Simulate all possible short/open faults • Build representative list – drop similar faults • Create ‘faulty’ OTA subcircuits

  7. amplitude -ve offset +ve offset Fault Insertion • Simulate filter with faulty OTA subcircuits • 1V p-p sinusoidal test signal in passband • Gain understanding of effects these faults have • Main effects of the detrimental faults: • Majority of faults change output by  200mV in some way

  8. Filter Outputs Fully Balanced Filter Test Mode BIST Analysis Window Detector Output Evaluation Test Output On-Chip Oscillator? Fully Balanced Equaliser Test Methodology • Sinusoid test signal in passband • Equaliser acts like filter at test frequency • Compare outputs of filter and equaliser Filter Inputs

  9. C (s) = = -d() - 2C Equaliser Block + - + gm gm - d + gm - + C Equaliser Design • First order OTA-C group delay equaliser • Much simpler circuit than filter itself • Matches filters of different types, orders and fc • Calculate C to match filter DC group delay • Signal inversion allows simpler analysis block design

  10. vdd vdd vdd vdd vdd vss vdd Filter vss Test output vss vdd vss vss vdd vss vss vss Equaliser Window Detector Output Evaluation Analysis Test Circuitry Design

  11. Filter output Equaliser output Analysis block output Test output FAULT- FREE 0.8 Amplitude (V) 0 0.8 4 Amplitude (V) 0 -4 0 10 20 Time (µs) Results: fault-free • The fault-free response: • Filter and equaliser outputs cancel resulting in negligible analysis block output • The analysis output lies completely in the acceptable window • Test output is LOW

  12. Filter output Equaliser output Analysis block output Test output FAULTY: output offset FAULTY: output reduced 0.8 0.8 Amplitude (V) Amplitude (V) 0 0 0.8 0.8 4 4 Amplitude (V) Amplitude (V) 0 0 -4 -4 0 0 10 10 20 20 Time (µs) Time (µs) Results: faulty • Faulty filter examples:

  13. Filter Test Conclusions • Analog BIST for fully-balanced OTA-C filters • Effective: short/open fault coverage of 99% • Simple: area overhead from layout is 20% • Almost no performance impact on filter • Low accuracy test frequency required • Tolerant to normal component variations • Methodology is applicable to many filter types

  14. Contact Reuben Wilcock Electronic Systems Design Department of Electronics and Computer Science University of Southampton United Kingdom rw01r@ecs.soton.ac.uk