SpaceWire 101 Seminar MAPLD 2006 SpaceWire origins and purpose From IEEE 1355 to ECSS-E-50-12A Ph. Armbruster TEC-ED

1. SpaceWire 101 Seminar MAPLD 2006 SpaceWire origins and purpose  From IEEE 1355 to ECSS-E-50-12A Ph. Armbruster TEC-ED Head of Data Systems Division ESA/ESTEC Introduction

2. Contents • A little bit of History – Transputers and Links • Serial links and Packet routing – Reference Architecture • From IEEE1355 to ECSS-E50-12A (SpaceWire) • SpaceWire Standard (SpW), a standard for Space Applications • SpaceWire Working Group – Meeting Schedule • ESA Developments • Perspectives Introduction

3. A little bit of History – Transputers The INMOS transputer was a pioneering concurrent computing microprocessor design of the 1980s from INMOS, a British semiconductor company based in Bristol. For some time in the late 1980s many considered the transputer to be the next great design for the future of computing. Today, this interesting chip is largely forgotten. Whilst ultimately a commercial failure, the transputer architecture was highly influential in provoking new ideas in computer architecture, several of which have re-emerged in different forms in modern systems. Source: http://en.wikipedia.org/wiki/Transputer The T9000 new packet-based link protocol was called DS-Link and later formed the basis of the IEEE 1355 serial interconnect standard (IEEE Std 1355-1995 Standard for Heterogeneous InterConnect (HIC) Low Cost Low Latency Scalable Serial Interconnect aka ISO/IEC 14575 DIS) Introduction

4. A little bit of History – Transputers and Links • DS-Link: Serial, asynchronous, Symmetrical, Flow-Controlled, Point-to-point Interface • • Data/Strobe, 100Mb/s+ • • Packet protocol, Routing switches • • Modular • • Scalable Introduction

5. Modules based on Hi-Rel components Modules based on COTS Optional Module Instrument Memory Module Context Saving Memory Data Compression Module Memory banks Memory banks I/O Module Instrument Telemetry Formatter /Encryption Module Transmitter SpW Router SpW Router CCD/APS Camera HIVAC Control Processor module Dedicated Processor module DSP Processor module RTC CAN bus Complex Instrument Instrument optional DPU Spacecraft control bus SpaceWire links Control bus/line Serial links and Packet routing – Reference Architecture This architecture is used by ESA as a reference for medium-range Data Handling Systems and the definition SpaceWire devices (SpW Router, SpW RTC, SMCS-SpW, …) Introduction

6. From IEEE1355 to ECSS-E50-12A (SpaceWire) • The IEEE1355 standard has been defined for commercial, ground based applications. • This standard has been revisited by space engineers, federated by the SpaceWire working group, in order to define a standard for space applications, covering: Links, nodes, routers and networks. • This work has been done from the physical level (e.g. LVDS, connectors, initialization state machine) up to higher level protocols (e.g. SpW-SnP-RMAP) and currently by mapping CCSDS-SOIS services and protocols on SpW networks. • SpaceWire is seen as an open standard. Its is supported by major agencies such as NASA, ESA, JAXA and RSA Introduction

7. SpaceWire Standard (SpW), a standard for Space Applications http://www.ecss.nl http://spacewire.esa.int Introduction

8. SpaceWire Working Group – Meeting Schedule • First SpW WG Mtg, 15th and 16th (AM) of September 2004 • Second SpW WG, 10th PM, 11th , 12th (AM) of November 2004  RMAP Draft B • Third SpW WG, 15th , 16th , 17th (AM) of February 2005  RMAP Draft C • Fourth SpW WG Meeting, 19th (PM), 20th and 21st (AM) of July 2005  RMAP Draft D • Fifth SpW WG Meeting, 15th (PM), 16th and 17th of November 2005  RMAP Draft E • Sixth SpW WG Meeting, 18th and 19th of May 2006  Focus on Implementation Issues • Seventh SpW Meeting – Inter-Agency Meeting 26th of September 2006 focus on • SpW Networks and Command and Control applications • SpaceFibre http://conferences.esa.int/01C25/ Introduction

9. SpW Working Group Steering Group (Mtg 7) Steering committee ESA (Chair) JAXA/ISAS NASA ROSCOSMOS Ph. Armbruster T. Takahashi G. Rakow A.G. Sukhoroukov M. Suess M. Nomachi (UoO) R. Schnurr Y. Shenin (UoStP) SpW WG Coordination. Coordinates/Approves PID allocations and supporting documents. Configuration management of in-preparation and published protocols. Steering committee supported by: S. Parkes (UoD) SpW, Standard(s) Editor SpW Working group contributors/participants: Agency engineering & projects representatives, Representatives from Industry, Experts Introduction

10. Instrument High Capacity Buffer High Capacity Buffer High Capacity Buffer I/O Module Telemetry Formatter/ Encryption Instrument Routing Matrix Routing Matrix Control Processor DedicatedDSP Processor DSP Processor Transmitter Instrument 1 DPU Instrument 2 DPU Spacecraft control bus ESA Developments Introduction

11. Perspectives • SpW is gaining momentum, used more and more • Devices under development to be made available as (ASSP) • Run a TopNet Pilot activity • Sustain development efforts at protocol level (e.g. for C&C and according to CCSDS-SOIS • Prepare the next step with SpaceFibre TopNet: Pilot activity, decentralised integration Involvement of different actors (industry, university, agency) in a pilot activity for decentralized integration of SpW-based data handling sub-systems that are geographically separated Introduction