Low-Voltage BiCMOS Circuits for High-Speed Data Links up to 80 Gb/s Tod Dickson University of Toronto June 24, 2005
Inductive peaking BiCMOS logic family reduces supply voltage CLDV2 LP = 3.1 IT2 Low-Voltage, Low-Power Techniques High-speed CML/ECL latch
2.5-V, 49-Gb/s Decision Circuit DFF 49-Gb/s Data In 49-Gb/s Data Out 49-GHz CLK Flip-flop core consumes 58 mW. 2 x 600mV output swing @ 49-Gb/s. Inductors smaller than bond pad.
80-Gb/s 231-1 PRBS Generator Die Photo 80-Gb/s output eye diagram Highest level of single-chip integration above 40-Gb/s Output Spectrum
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver First silicon amplifier with gain above 90-GHz. Adjustable pre-emphasis for operation up to 80-Gb/s Boosts high-frequency content to compensate for line losses. Output match S22 < -10dB up to 94 GHz.