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TK 6123 COMPUTER ORGANISATION & ARCHITECTURE

TK 6123 COMPUTER ORGANISATION & ARCHITECTURE. Lecture 9: Input/output. Contents. This lecture will discuss: Computer Modules . Input Output Techniques Interrupts. Introduction.

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TK 6123 COMPUTER ORGANISATION & ARCHITECTURE

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  1. TK 6123COMPUTER ORGANISATION & ARCHITECTURE Lecture 9: Input/output

  2. Contents • This lecture will discuss: • Computer Modules. • Input Output Techniques • Interrupts.

  3. Introduction • I/O operations take up a lot of computer time - much CPU time is wasted waiting for the completion of the I/O task. • Several different techniques are combined to resolve the problem of synchronising and handling I/O between a variety of different I/O devices operating with different quantities of data at different speeds.

  4. Connecting • All the units must be connected • Different type of connection for different type of unit • Memory • Input/Output • CPU

  5. Computer Modules

  6. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing

  7. Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer

  8. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control)

  9. CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts

  10. Input/Output Problems • Wide variety of peripherals • Delivering different amounts of data • At different speeds • In different formats • All slower than CPU and RAM • Need I/O modules

  11. Input/Output Module • Interface to CPU and Memory • Interface to one or more peripherals

  12. Generic Model of I/O Module

  13. External Devices • Human readable • Screen, printer, keyboard • Machine readable • Monitoring and control • Communication • Modem • Network Interface Card (NIC)

  14. External Device Block Diagram

  15. I/O Module Function • Control & Timing • CPU Communication • Device Communication • Data Buffering • Error Detection

  16. I/O Steps • CPU checks I/O module device status • I/O module returns status • If ready, CPU requests data transfer • I/O module gets data from device • I/O module transfers data to CPU • Variations for output, DMA, etc.

  17. I/O Module Diagram

  18. I/O Module Decisions • Hide or reveal device properties to CPU • Support multiple or single device • Control device functions or leave for CPU

  19. Input Output Techniques • Programmed • Interrupt driven • Direct Memory Access (DMA)

  20. Three Techniques for Input of a Block of Data

  21. Programmed I/O • CPU has direct control over I/O • Sensing status • Read/write commands • Transferring data • CPU waits for I/O module to complete operation • Wastes CPU time

  22. Programmed I/O - detail • CPU requests I/O operation • I/O module performs operation • I/O module sets status bits • CPU checks status bits periodically - polling • I/O module does not inform CPU directly • I/O module does not interrupt CPU • CPU may wait or come back later

  23. I/O Commands • CPU issues address • Identifies module (& device if >1 per module) • CPU issues command • Control - telling module what to do • e.g. spin up disk • Test - check status • e.g. power? Error? • Read/Write • Module transfers data via buffer from/to device

  24. Addressing I/O Devices • Under programmed I/O data transfer is very like memory access (CPU viewpoint) • Each device given unique identifier • CPU commands contain identifier (address)

  25. I/O Mapping • Memory mapped I/O • Devices and memory share an address space • I/O looks just like memory read/write • No special commands for I/O • Large selection of memory access commands available • Isolated I/O • Separate address spaces • Need I/O or memory select lines • Special commands for I/O • Limited set

  26. Memory Mapped and Isolated I/O

  27. Interrupt Driven I/O • Overcomes CPU waiting • No repeated CPU checking of device • I/O module interrupts when ready

  28. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Allows to time share the CPU between several different programs at once. • Modern computers provide interrupt capability by providing special control lines to the central processor known as interrupt lines. • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error

  29. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

  30. Transfer of Control via Interrupts

  31. Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt

  32. Multiple Interrupts - Sequential

  33. Multiple Interrupts – Nested

  34. Interrupt Driven I/O: Basic Operation • CPU issues read command • I/O module gets data from peripheral whilst CPU does other work • I/O module interrupts CPU • CPU requests data • I/O module transfers data

  35. Simple Interrupt Processing

  36. CPU Viewpoint • Issue read command • Do other work • Check for interrupt at end of each instruction cycle • If interrupted:- • Save context (registers) • Process interrupt • Fetch data & store

  37. Changes in Memory and Registers for an Interrupt

  38. Design Issues • How do you identify the module issuing the interrupt? • How do you deal with multiple interrupts? • i.e. an interrupt handler being interrupted The interrupt handler (or interrupt service routine, ISR) - determines appropriate course of action. This process is known as servicing the interrupt.

  39. Identifying Interrupting Module (1) • Different line for each module • Limits number of devices • A vectored interrupt is used, in which the address of the interrupting device is included as part of the interrupt. • Faster, but requires additional hardware to implement. • Software poll • Use a general interrupt that is shared by all devices. • CPU asks each module in turn • Slow

  40. Vectored Interrupt vs Polled Interrupt Vectored Interrupt Polled Interrupt

  41. Identifying Interrupting Module (2) • Daisy Chain or Hardware poll • Interrupt Acknowledge sent down a chain • Module responsible places vector on bus • CPU uses vector to identify handler routine • Bus Master • Module must claim the bus before it can raise interrupt

  42. Multiple Interrupts • Each interrupt line has a priority • Higher priority lines can interrupt lower priority lines • If bus mastering, only current master can interrupt

  43. Direct Memory Access • Interrupt driven and programmed I/O require active CPU intervention • Transfer rate is limited • CPU is tied up • DMA is the answer. • DMA is more efficient for transferring large volumes of data.

  44. DMA Function • Additional Module (hardware) on bus • DMA controller takes over from CPU for I/O operations.

  45. Typical DMA Module Diagram

  46. DMA Operation • CPU tells DMA controller:- • Read/Write • Device address • Starting address of memory block for data • Amount of data to be transferred • CPU carries on with other work • DMA controller deals with transfer • DMA controller sends interrupt when finished

  47. DMA Transfer: Cycle Stealing • DMA controller takes over bus for a cycle • Transfer of one word of data • Not an interrupt • CPU does not switch context • CPU suspended just before it accesses bus • i.e. before an operand or data fetch or a data write • Slows down CPU but not as much as CPU doing transfer.

  48. Fly-By • While DMA using buses processor idle • Processor using bus, DMA idle • Known as fly-by DMA controller • Data does not pass through and is not stored in DMA chip • DMA only between I/O port and memory • Not between two I/O ports or two memory locations • Can do memory to memory via register

  49. I/O Channels • I/O devices getting more sophisticated • e.g. 3D graphics cards • CPU instructs I/O controller to do transfer • I/O controller does entire transfer • Improves speed • Takes load off CPU • Dedicated processor is faster

  50. Thank youQ & A

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