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Low Noise Design

Low Noise Design. EMC Test Summary - In house. Spectrum with TEM Cell Method - 3V, 4MHz. R8C/11. MCU-T. dB. MCU-F. MCU-A. Confidential. KHz. Outline. 1. Testing and Standards a. Noise types b. Standards and Testing c. Renesas Testing and facilities 2. Some Noise Basics

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Low Noise Design

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  1. Low Noise Design Company Confidential

  2. EMC Test Summary - In house • Spectrum with TEM Cell Method - 3V, 4MHz R8C/11 MCU-T dB MCU-F MCU-A Company Confidential Confidential KHz

  3. Outline 1. Testing and Standards a. Noise types b. Standards and Testing c. Renesas Testing and facilities 2. Some Noise Basics 3. System Level Noise Countermeasures 4. IC Level Design Considerations and Countermeasures Company Confidential

  4. Noise Concerns • 4 basic areas of noise concerns • Emissions - Test requirements for: • Radiated • Conducted • Susceptibility - Test requirements for : • Radiated • Conducted • Impulse and Transient • Supply voltage variations • ESD - Test requirements for : • Contact discharge • Air discharge • Signal Integrity • (no standards) - user must determine appropriate testing Company Confidential

  5. Standards and Renesas EMI Activities Company Confidential

  6. System Level TestingEmissions Specifications • Specifications for Radiated Emissions • FCC Part 15 • CISPR 22 • Test Methods for Radiated Emissions • Anechoic Chamber • Open Air Test Site (OATS) • Test Methods for Conducted Emissions • Current Probes • Capacitive Clamps Anechoic Room Current Probe Company Confidential

  7. System Level Testing Susceptibility Specifications • IEC 61000-4 • Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test • Part 4-3: Testing and measurement techniques - Radiated, radio-frequency, electromagnetic field immunity test • Part 4-4: Testing and measurement techniques - Electrical fast transient/burst immunity test • Part 4-5: Testing and measurement techniques - Surge immunity test • Part 4-6: Testing and measurement techniques - Immunity to conducted disturbances, induced by radio-frequency fields • Part 4-11: Testing and measurement techniques - Voltage dips, short interruptions and voltage variations immunity tests • Part 4-12: Testing and measurement techniques - Oscillatory waves immunity test • Part 4-14: Testing and measurement techniques - Voltage fluctuation immunity test • Most of these specifications have corresponding system level tests (and additional tests) specified by IEEE, ANSI, SAE and other local authorities • These tests typically only test lines that leave the “system” enclosure or can be contacted by user Company Confidential

  8. System Level Testing • Though these system level tests are important it is not always easy to correlate the performance in these test to MCU characteristics • Poor system level design can make any MCU perform poorly in emissions or susceptibility testing • IEC is working on standards which can be used to standardize noise testing at the IC level Company Confidential

  9. IC Level TestingIEC Emissions Specifications Document Number Date issued Status Title and Std. code Company Confidential

  10. IC Level TestingIEC Immunity test method [IEC62132] Latest document Status Date of Issue Document number and Title [IEC62215] Latest document Status Date of Issue Document number and Title Company Confidential

  11. IC Level TestingRenesas Involvement Renesas Company Confidential

  12. EMC Lab. in Renesas Technology • Renesas built own EMC facility in Musashi design center for investigating reduced emission and improved Immunity. Near field scanner Electric Shielded room Company Confidential

  13. Equipment in Renesas EMC Lab(1) • Unique Near-field scanner is now on duty in Renesas EMC Lab. • Measure both H-field and E-field simultaneously while the previous one was effective only for H-field. • H-field distribution relates to intensity of noise current at the frequency of interest. • E- field distribution relates to high impedance traces or resonating planes • Faraday Cage Workbench (IEC 61967-5, [IEC 62132-5]) • Common mode voltage of modules can be measured. • Similar result as CISPR-25 or antenna techniques in anechoic chamber can be obtained quickly Near field scanner Faraday Cage Workbench Company Confidential

  14. Equipment in Renesas EMC Lab(2) • Direct Power Injection method (IEC 62132-4) • Automated evaluation system is under construction. • High voltage generator and injection gun for ESD test (IEC 61000-4) • High-speed, Long memory Oscilloscope. • Malfunction of CPU against injected voltage can be investigated. • Voltage fluctuations around CPU or variations on Power/Gnd rails on PCB can be measured by High-Z probes (4ch). ESD gun and DUT on the table Direct Power Injection system ESD evaluation area Company Confidential

  15. EMI measurement method for ICs (1) Vcc Vcc Vcc 950Ω IC 49Ω in 50Ω IC 50Ω 1K Ohm ex. vn in 50Ω 1Ω IC • Supply current measurement techniques IS IS (1) VDE Method (2) Magnetic Probe (3) Vcc/Gnd Voltage Company Confidential

  16. EMI measurement method for Ics (2) Vcc 50Ω 50Ω vn u • CM voltage, EM radiation measurement techniques IS DTS CDV (4) Faraday Cage (5) TEM Cell (6) Loop Probe Company Confidential

  17. Some Results Noise current measurement for SH7055RF and NF-probe Analysis @80MHz FM FM VDE Method (IEC 61967-4) Pitch : 2mm Height : 5mm （above board） Scanned Area 58dB 46dB 40MHz (10MHz×4) Program execute Vcc = 3.3V, PVcc = 5.0V Decoupling Capacitor without Decoupling Capacitor with Decoupling Capacitor Company Confidential

  18. Some Results Noise current measurement for SH7055SF Scanned Area FM FM VDE Method (IEC 61967-4) and NF-probe Analysis Pitch : 2mm Height : 5mm （above board） @80MHz 58dB 46dB 42dB 24dB 40MHz (10MHz×4) Program execute Vcc = 3.3V, PVcc = 5.0V VCL Capacitor Decoupling Capacitor without Decoupling Capacitor with Decoupling Capacitor Company Confidential

  19. EMI Basics Company Confidential

  20. EMI BasicsH-Field or Differential Emissions Magnetic or H - Field emissions are the result of current flow in traces • Magnitude of the radiated field is • EMI = (k * I * F2 * A)/d • k is a constant based on many physical parameters • I is the current flowing in the loop conductors • F is the frequency of the current • A is the area enclosed by the current carrying conductors • d is the distance of the receptor from the loop I Load Loop Area Company Confidential

  21. EMI Basics E Field or Common Mode E - Field emissions result due to in-phase currents on two lines or voltage potentials on traces Common mode noises are very effective radiators Sources of common mode noise a. Noisy grounds b. Unbalanced signal and return paths Noise Source (e.g. Clock Circuit) Common Mode Noise due to pickup + noise Signal Line + noise Return Line (GND) Company Confidential

  22. EMI BasicsEMI Spectrum of a squarewave • Corner frequency set by 1/ t where t is the risetime of the waveform • On a 1 MHz squarewave, changing the rise time from 5 nSec to 20 nSec reduces the amplitude of the 5th harmonic by approximately 6dB Company Confidential

  23. EMI BasicsCross-talk Transmitter Line Driving Device Driving Device Parasitic Inductances Parasitic Capacitances Receptor Line • Crosstalk occurs due to parasitic capacitances and inductances in circuits • Capacitive crosstalk is dominant when impedance is high, inductive coupling dominates when impedances are low • Adding a impedance from receptor line to ground can reduce capacitive crosstalk • Reducing edge rates by adding series resistance or line-to-ground capacitance in transmitter line can reduce crosstalk Company Confidential

  24. EMI BasicsImpedance Matching • A reflection occurs at any discontinuity in impedance Receiver Trasmitter Zout Zi Z0 Vs • When the impedance increases the reflected pulse is in the same direction as the incident wave • When the impedance decreases the reflected pulse is opposite the incident wave Company Confidential

  25. EMI BasicsImpedance Matching • To prevent the reflection a termination impedance is placed at the far end of the line. Zm // Zi should equal the characteristic impedance Zo Receiver Trasmitter No Reflection Zout Zi Z0 Zm Vs • Transmission line analysis and impedance matching are generally only required for “long” lines • A rule of thumb is a for ar a 1 nSec rise time any trace over 3” is considered long(on FR4 board) Company Confidential

  26. System Level Design Considerations Company Confidential

  27. System DesignBypassing • Mount bypass capacitors as close as possible to device • Keep Vcc and Ground leads equal lengths • Keeping the capacitor close minimizes the loop area enclosed by the high frequency currents • It is important to keep the Vcc and Gnd trace lengths equal to minimize common mode signals • Use multiple bypass capacitors for different frequencies. • Inductance in Vcc lead can minimize emissions • A ceramic bypass capacitor and high frequency aluminum or tantalum bulk capacitor creates a very effective bypass • Adding series inductance in the Vcc lead increases the effectiveness of the bypass capacitors Company Confidential

  28. System DesignBypass Capacitor 1000 Bypass capacitor working area 100 0.05µF Ceramic 0.1µF Mylar 4.7µF Tantalum Electrolytic Impedance (IΩI) 10 1 0.05µF Feed through 0.1 5mm Wire 100µF Aluminum Electrolytic Ideal 0.05µF Capacitor 0.01 10k 100k 1M 10M 100M 1G 1k Frequency (Hz) • Use appropriate bypass capacitors • Consider using feedthrough caps schematic Equivalent circuit Company Confidential

  29. System Design Bus Connections • Use serial connections to peripherals instead of parallel connections • Using serial connections minimizes the total number of line and the total area of conductor which can pickup or emit noise • Use single chip devices when possible • On chip flash and RAM minimizes the trace length to these devices • SIP packages provide lower noise than discrete systems Company Confidential

  30. System DesignPower and Ground Routing • If multilayer boards are not used layout power in loop or net layout • Objective is to minimize ground and Vcc variations along leads. Voltage variations lead to common mode noise • MCU becomes a star point with a loop connecting the spokes • When loop patterns are not practical to peripherals route Vcc and ground parallel and make lengths equal • Routing Vcc and Gnd parallel to each other minimizes loop area and keeps signals differential • Equal lengths minimizes common mode noise Company Confidential

  31. System DesignResistors • On circuits that have current limiting resistors place the resistors close the MCU • By placing the resistor next to the MCU any noise picked up by the trace will not reach the MCU • Resistor also forms a low pass filter with trace for noise emitted from MCU • When possible place Damping/Slew control resistors on long leads • Adding series resistance slows rise times • Resistance also damps any oscillatory waves • Amount of resistance depends on circuit but a few hundred ohms is usually effective Company Confidential

  32. System Design MCU Selection • Select a microcontroller that produces low levels of EMI and has good noise immunity • In the next section we will look at some of the design techniques that are used to make Renesas MCU’s superior in EMI/EMS performance Company Confidential

  33. Designing Superior EMI/EMS MCUs Company Confidential

  34. M16C Family Emission Noise CISC-A CISC-C RISC-A M16C/62 (16MHz) M16C/80 (20MHz) M32C/83 (30MHz) Company Confidential

  35. EMC Test Summary - In house MCU – T: 4MHz, 3V R8C/11- 4MHz, 5V • Electromagnetic field probe test Spectrum MCU –A: 4MHz, 5V MCU – F: 4MHz, 5V Confidential Company Confidential

  36. Noise Control -1 The same design improvements that counter EMI emissions help reduce EMI susceptibility • EMI basic noise reduction : • Keep all signals differential with small current loops • This can be visualized as the two closely coupled fluxes canceling each other • Minimize any common mode signals since they radiate very effectively • Do this by balancing lengths of signal paths and keeping signal and return equally spaced • Minimize overshoot and high speed transitions of signals + signal Flux lines equal and opposite return Company Confidential

  37. Noise Control - 2 • EMC sensitivity reduction : • Keep all signals lines differential with small current loops • Signal lines will receive equal flux concentration which results in common mode voltage induced. These small common mode voltages do not upset operation • Balance lengths of signal paths and keep signal and return equally spaced so all noise pickup is common mode • Minimize overshoot and high speed transitions of signals which can cause crosstalk problems + noise No Net Voltage Influence Flux lines equal and opposite + noise Company Confidential

  38. Designing Superior EMC MCUsMultiple Clock Drive Levels A “H” B A B • Changing the driving capability of the clock oscillation circuit allows fast,reliable start-up with noise caused by over-driving crystal eliminated in steady-state condition • Multiple levels simplify oscillator component selection since start-up is provided by high drive mode Static-stateoscillation Startoscillation “L” Low Drive Mode High Drive Mode Company Confidential

  39. Designing Superior EMC MCUsBuffer Design Considerations 1 Vcc Vcc Vcc GND IN OUT IN OUT GND GND Control drive capacity of the internal and port buffer transistors • Excessive drive results in overshoot and ringing which increase emissions and can result in signal integrity issues on the board Control the slew rate of the drive signals • The high frequency content of the signal is directly related to the rise and fall time. • Limiting these rates reduces the high frequency emissions and cross-talk Company Confidential

  40. Designing Superior EMC MCUsBuffer Design Considerations 2 Vcc Vcc P-ch P-ch Control Circuit N-ch N-ch GND GND Internal External t1 t1 t2 Eliminate dash currents in output buffers • Drive signals to the N channel and P channel transistors are shaped to prevent both from conduction at the same time • This pass-through or dash current results in short duration high current spikes which increases emissions and increases average power consumption • Control the switching of the output buffers • Port buffer switch times are controlled. • Buffer switching is intentionally skewed a very small amount to minimize current spiking Output terminal Synchronizedswitching Time-shiftedswitching Company Confidential

  41. Designing Superior EMC MCUsBypass Capacitance IN OUT Vcc GND N + P + P + N + N + P + N P P - Vcc Vcc IN OUT IN OUT GND GND Noise absorption as common mode Vcc Vcc Pin layout simplifies putting bypass capacitor at best position Long Lead length Parasitic capacitor GND GND Wiring inductance • An innovative layout is used to add internal capacitance without affecting die area • Typical device internal parasitic capacitance is <100 pF in a device • This layout technique increase internal capacitance into range of 4000-5000 pF • These capacitances are very effective bypass devices since they control local currents Vcc & GND terminals are located for optimum bypass capacitor effect • Arranging Vcc and Gnd close together allows maximizing effectiveness of the external bypass capacitor • The internal layout of these two lines is also controlled to create a common mode filter Company Confidential

  42. Designing Superior EMC MCUsInput Protection and Signal Integrity Input pins have analog noise filters and schmitt buffers • RC input filter reduces high frequency noise • Schmitt gate reduces lower frequency variations • Clamp diodes prevent overshoot or undershoot from propagating into device Company Confidential

  43. Designing Superior EMC MCUsPower and Ground Layout • Separate power supply paths to different noise sources • Separating power supply lines prevents mixing different types of noise • Separate power lines allows sizing power lines for each type of block Electrically Separated Supply Lines Internal Noise Sources Company Confidential

  44. Designing Superior EMC MCUsPin Arangement for Vcc, GND, Oscillator Bypass capacitor (~0.01µF) VCC VSS M16C Microcontroller Bypasscapacitor (~0.01µF) BYTE CNVSS XCIN XCOUT /RESET XOUT VSS XIN VCC /NMI Sheet pattern of VCC AVSS VREF AVCC Sheet pattern of GND Oscillation capacitors (symetrically placed) Bypass capacitor (~0.01µF) Tantalum capacitor Oscillation capacitors (symetrically placed) ResetIC Capacitor for RESET (1000pF) GND VCC • Pin arrangement for Reset, Clock and power set to minimize noise affects • Pin configuration of oscillator pins allow symmetrical placement of components. This minimizes common mode noise generation • Reset is very close to power this allows placing a noise rejection capacitor with very short lead from Reset to Gnd • Having Vcc and Vss pins on both sides allows symmetrical power planes inside the device Company Confidential

  45. Not Designing Superior EMC MCUs clock Analog Vdd,Gnd Vss & Vdd Company Confidential

  46. Noise Free/Immune - Low EMI/EMS Example of an M16C-based circuit board Example of a noise preventing circuit MCU Power supply ferrite beads placed on the VCC pin Control signal lines protected with noise filters and capacitors Capacitors and resistors unnecessary Data and address buses protectedwith dumping resistors Up to 60% Better EMI Performance Company Confidential

  47. Renesas Technology America, Inc. 47 Company Confidential

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